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`timescale 1ns / 1ps
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/*
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* File : EXMEM_Stage.v
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* Project : University of Utah, XUM Project MIPS32 core
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* Creator(s) : Grant Ayers (ayers@cs.utah.edu)
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*
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* Modification History:
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* Rev Date Initials Description of Change
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* 1.0 9-Jun-2011 GEA Initial design.
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* 2.0 26-Jul-2012 GEA Many updates have been made.
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*
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* Standards/Formatting:
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* Verilog 2001, 4 soft tab, wide column.
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*
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* Description:
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* The Pipeline Register to bridge the Execute and Memory stages.
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*/
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module EXMEM_Stage(
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input clock,
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input reset,
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input EX_Flush,
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input EX_Stall,
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input M_Stall,
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// Control Signals
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input EX_Movn,
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input EX_Movz,
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input EX_BZero,
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input EX_RegWrite, // Future Control to WB
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input EX_MemtoReg, // Future Control to WB
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input EX_ReverseEndian,
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input EX_LLSC,
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input EX_MemRead,
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input EX_MemWrite,
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input EX_MemByte,
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input EX_MemHalf,
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input EX_MemSignExtend,
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input EX_Left,
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input EX_Right,
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// Exception Control/Info
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input EX_KernelMode,
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input [31:0] EX_RestartPC,
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input EX_IsBDS,
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input EX_Trap,
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input EX_TrapCond,
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input EX_M_CanErr,
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// Data Signals
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input [31:0] EX_ALU_Result,
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input [31:0] EX_ReadData2,
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input [4:0] EX_RtRd,
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// ------------------
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output reg M_RegWrite,
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output reg M_MemtoReg,
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output reg M_ReverseEndian,
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output reg M_LLSC,
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output reg M_MemRead,
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output reg M_MemWrite,
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output reg M_MemByte,
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output reg M_MemHalf,
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output reg M_MemSignExtend,
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output reg M_Left,
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output reg M_Right,
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output reg M_KernelMode,
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output reg [31:0] M_RestartPC,
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output reg M_IsBDS,
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output reg M_Trap,
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output reg M_TrapCond,
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output reg M_M_CanErr,
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output reg [31:0] M_ALU_Result,
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output reg [31:0] M_ReadData2,
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output reg [4:0] M_RtRd
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);
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/***
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The purpose of a pipeline register is to capture data from one pipeline stage
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and provide it to the next pipeline stage. This creates at least one clock cycle
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of delay, but reduces the combinatorial path length of signals which allows for
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higher clock speeds.
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All pipeline registers update unless the forward stage is stalled. When this occurs
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or when the current stage is being flushed, the forward stage will receive data that
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is effectively a NOP and causes nothing to happen throughout the remaining pipeline
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traversal. In other words:
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A stall masks all control signals to forward stages. A flush permanently clears
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control signals to forward stages (but not certain data for exception purposes).
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***/
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// Mask of RegWrite if a Move Conditional failed.
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wire MovcRegWrite = (EX_Movn & ~EX_BZero) | (EX_Movz & EX_BZero);
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always @(posedge clock) begin
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M_RegWrite <= (reset) ? 0 : ((M_Stall) ? M_RegWrite : ((EX_Stall | EX_Flush) ? 0 : EX_RegWrite));
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M_RegWrite <= (reset) ? 0 : ((M_Stall) ? M_RegWrite : ((EX_Stall | EX_Flush) ? 0 : ((EX_Movn | EX_Movz) ? MovcRegWrite : EX_RegWrite)));
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M_MemtoReg <= (reset) ? 0 : ((M_Stall) ? M_MemtoReg : EX_MemtoReg);
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M_ReverseEndian <= (reset) ? 0 : ((M_Stall) ? M_ReverseEndian : EX_ReverseEndian);
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M_LLSC <= (reset) ? 0 : ((M_Stall) ? M_LLSC : EX_LLSC);
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M_MemRead <= (reset) ? 0 : ((M_Stall) ? M_MemRead : ((EX_Stall | EX_Flush) ? 0 : EX_MemRead));
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M_MemWrite <= (reset) ? 0 : ((M_Stall) ? M_MemWrite : ((EX_Stall | EX_Flush) ? 0 : EX_MemWrite));
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M_MemByte <= (reset) ? 0 : ((M_Stall) ? M_MemByte : EX_MemByte);
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M_MemHalf <= (reset) ? 0 : ((M_Stall) ? M_MemHalf : EX_MemHalf);
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M_MemSignExtend <= (reset) ? 0 : ((M_Stall) ? M_MemSignExtend : EX_MemSignExtend);
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M_Left <= (reset) ? 0 : ((M_Stall) ? M_Left : EX_Left);
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M_Right <= (reset) ? 0 : ((M_Stall) ? M_Right : EX_Right);
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M_KernelMode <= (reset) ? 0 : ((M_Stall) ? M_KernelMode : EX_KernelMode);
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M_RestartPC <= (reset) ? 32'b0 : ((M_Stall) ? M_RestartPC : EX_RestartPC);
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M_IsBDS <= (reset) ? 0 : ((M_Stall) ? M_IsBDS : EX_IsBDS);
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M_Trap <= (reset) ? 0 : ((M_Stall) ? M_Trap : ((EX_Stall | EX_Flush) ? 0 : EX_Trap));
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M_TrapCond <= (reset) ? 0 : ((M_Stall) ? M_TrapCond : EX_TrapCond);
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M_M_CanErr <= (reset) ? 0 : ((M_Stall) ? M_M_CanErr : ((EX_Stall | EX_Flush) ? 0 : EX_M_CanErr));
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M_ALU_Result <= (reset) ? 32'b0 : ((M_Stall) ? M_ALU_Result : EX_ALU_Result);
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M_ReadData2 <= (reset) ? 32'b0 : ((M_Stall) ? M_ReadData2 : EX_ReadData2);
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M_RtRd <= (reset) ? 5'b0 : ((M_Stall) ? M_RtRd : EX_RtRd);
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end
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endmodule
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