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[/] [mips_16/] [trunk/] [bench/] [EX_stage/] [alu_tb_0.v] - Blame information for rev 2

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////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   18:23:03 02/08/2012
// Design Name:   alu
// Module Name:   F:/Projects/My_MIPS/mips_16/bench/EX_stage/alu_tb_0.v
// Project Name:  mips_16
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: alu
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
`timescale 1ns / 1ps
`include "mips_16_defs.v"
 
module alu_tb_0_v;
 
        // Inputs
        reg [15:0] a;
        reg [15:0] b;
        reg [2:0] cmd;
 
        // Outputs
        wire [15:0] r;
        reg [15:0] rand;
        integer i;
 
        // Instantiate the Unit Under Test (UUT)
        alu uut (
                .a(a),
                .b(b),
                .cmd(cmd),
                .r(r)
        );
 
        initial begin
                // Initialize Inputs
                a = 0;
                b = 0;
                cmd = 0;
 
                // Wait 100 ns for global reset to finish
                #100;
 
                // Add stimulus here
                i=0;
                while(i<10) begin
                        test_NC;
                        test_ADD;
                        test_SUB;
                        test_AND;
                        test_OR;
                        test_XOR;
                        test_SL;
                        test_SR;
                        test_SRU;
                        i = i+1;
                end
                $stop;
                $finish;
        end
 
        task test_NC;
                begin
                        $write(" ALU_NC \t");
                        a = $random % 32768;
                        b = $random % 32768;
                        cmd = `ALU_NC;
                        #10
                        // if(r == 16'bxxxxxxxxxxxxxxxx) 
                                $write("ok ");
                        // else
                                // $write("error @ %t , get %d, expect %d", $time, r, a b);
                        $write("\n");
                end
        endtask
 
        task test_ADD;
                begin
                        $write(" ALU_ADD \t");
                        a = $random % 32768;
                        b = $random % 32768;
                        cmd = `ALU_ADD;
                        #10
                        if(r == a + b)
                                $write("ok ");
                        else
                                $write("error @ %t , get %d, expect %d", $time, r, a+b);
                        $write("\n");
                end
        endtask
 
        task test_SUB;
                begin
                        $write(" ALU_SUB \t");
                        a = $random % 32768;
                        b = $random % 32768;
                        cmd = `ALU_SUB;
                        #10
                        if(r == a - b)
                                $write("ok ");
                        else
                                $write("error @ %t , get %d, expect %d", $time, r, a-b);
                        $write("\n");
                end
        endtask
 
        task test_AND;
                begin
                        $write(" ALU_AND \t");
                        // a = $random % 32768;
                        // b = $random % 32768;
                        a = 16'b0101010101010101;
                        b = 16'b1010101001010101;
                        cmd = `ALU_AND;
                        #10
                        if(r == 16'b0000000001010101)
                        // if(r == 16'd85) 
                                $write("ok ");
                        else
                                $write("error @ %t , get %d, expect %d", $time, r, a&b);
                        $write("\n");
                end
        endtask
 
        task test_OR;
                begin
                        $write(" ALU_OR \t");
                        a = $random % 32768;
                        b = $random % 32768;
                        cmd = `ALU_OR;
                        #10
                        if(r == a | b)
                                $write("ok ");
                        else
                                $write("error @ %t , get %d, expect %d", $time, r, a|b);
                        $write("\n");
                end
        endtask
 
        task test_XOR;
                begin
                        $write(" ALU_XOR \t");
                        a = $random % 32768;
                        b = $random % 32768;
                        cmd = `ALU_XOR;
                        #10
                        if(r == a ^ b)
                                $write("ok ");
                        else
                                $write("error @ %t , get %d, expect %d", $time, r, a^b);
                        $write("\n");
                end
        endtask
 
        task test_SL;
                begin
                        $write(" ALU_SL \t");
                        a = $random % 32768;
                        b = {$random} % 16;
                        cmd = `ALU_SL;
                        #10
                        if(r == a << b)
                                $write("ok ");
                        else
                                $write("error @ %t , get %d, expect %d", $time, r, a<<b);
                        $write("\n");
                end
        endtask
 
        // task test_SR;
                // begin
                        // $write(" ALU_SR \t");
                        // a = $random % 32768;
                        // b = {$random} % 16;
                        // cmd = `ALU_SR;
                        // #10
                        // if(r == a / 2**b ) 
                                // $write("ok ");
                        // else
                                // $write("error @ %t , get %d, expect %d", $time, r, (a/(2**b)));
                        // $write("\n");
                // end
        // endtask
        task test_SR;
                begin
                        $write(" ALU_SR \t");
                        a = 16'b1111000011110000;
                        b = 7;
                        cmd = `ALU_SR;
                        #10
                        if(r == 16'b1111111111100001 )
                                $write("ok ");
                        else
                                $write("error @ %t , get %d, expect %d", $time, r, 16'b1111111111100001);
                        $write("\n");
                end
        endtask
 
        task test_SRU;
                begin
                        $write(" ALU_SRU \t");
                        a = $random % 32768;
                        b = {$random} % 16;
                        cmd = `ALU_SRU;
                        #10
                        if(r == a >> b )
                                $write("ok ");
                        else
                                $write("error @ %t , get %d, expect %d", $time, r, a >> b);
                        $write("\n");
                end
        endtask
 
endmodule
 

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Subversion Repositories mips_16

[/] [mips_16/] [trunk/] [bench/] [EX_stage/] [alu_tb_0.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	Doyya	`////////////////////////////////////////////////////////////////////////////////`
2			`// Company:`
3			`// Engineer:`
4			`//`
5			`// Create Date: 18:23:03 02/08/2012`
6			`// Design Name: alu`
7			`// Module Name: F:/Projects/My_MIPS/mips_16/bench/EX_stage/alu_tb_0.v`
8			`// Project Name: mips_16`
9			`// Target Device:`
10			`// Tool versions:`
11			`// Description:`
12			`//`
13			`// Verilog Test Fixture created by ISE for module: alu`
14			`//`
15			`// Dependencies:`
16			`//`
17			`// Revision:`
18			`// Revision 0.01 - File Created`
19			`// Additional Comments:`
20			`//`
21			`////////////////////////////////////////////////////////////////////////////////`
22			`timescale 1ns / 1ps
23			`include "mips_16_defs.v"
24
25			`module alu_tb_0_v;`
26
27			`// Inputs`
28			`reg [15:0] a;`
29			`reg [15:0] b;`
30			`reg [2:0] cmd;`
31
32			`// Outputs`
33			`wire [15:0] r;`
34			`reg [15:0] rand;`
35			`integer i;`
36
37			`// Instantiate the Unit Under Test (UUT)`
38			`alu uut (`
39			`.a(a),`
40			`.b(b),`
41			`.cmd(cmd),`
42			`.r(r)`
43			`);`
44
45			`initial begin`
46			`// Initialize Inputs`
47			`a = 0;`
48			`b = 0;`
49			`cmd = 0;`
50
51			`// Wait 100 ns for global reset to finish`
52			`#100;`
53
54			`// Add stimulus here`
55			`i=0;`
56			`while(i<10) begin`
57			`test_NC;`
58			`test_ADD;`
59			`test_SUB;`
60			`test_AND;`
61			`test_OR;`
62			`test_XOR;`
63			`test_SL;`
64			`test_SR;`
65			`test_SRU;`
66			`i = i+1;`
67			`end`
68			`$stop;`
69			`$finish;`
70			`end`
71
72			`task test_NC;`
73			`begin`
74			`$write(" ALU_NC \t");`
75			`a = $random % 32768;`
76			`b = $random % 32768;`
77			cmd = `ALU_NC;
78			`#10`
79			`// if(r == 16'bxxxxxxxxxxxxxxxx)`
80			`$write("ok ");`
81			`// else`
82			`// $write("error @ %t , get %d, expect %d", $time, r, a b);`
83			`$write("\n");`
84			`end`
85			`endtask`
86
87			`task test_ADD;`
88			`begin`
89			`$write(" ALU_ADD \t");`
90			`a = $random % 32768;`
91			`b = $random % 32768;`
92			cmd = `ALU_ADD;
93			`#10`
94			`if(r == a + b)`
95			`$write("ok ");`
96			`else`
97			`$write("error @ %t , get %d, expect %d", $time, r, a+b);`
98			`$write("\n");`
99			`end`
100			`endtask`
101
102			`task test_SUB;`
103			`begin`
104			`$write(" ALU_SUB \t");`
105			`a = $random % 32768;`
106			`b = $random % 32768;`
107			cmd = `ALU_SUB;
108			`#10`
109			`if(r == a - b)`
110			`$write("ok ");`
111			`else`
112			`$write("error @ %t , get %d, expect %d", $time, r, a-b);`
113			`$write("\n");`
114			`end`
115			`endtask`
116
117			`task test_AND;`
118			`begin`
119			`$write(" ALU_AND \t");`
120			`// a = $random % 32768;`
121			`// b = $random % 32768;`
122			`a = 16'b0101010101010101;`
123			`b = 16'b1010101001010101;`
124			cmd = `ALU_AND;
125			`#10`
126			`if(r == 16'b0000000001010101)`
127			`// if(r == 16'd85)`
128			`$write("ok ");`
129			`else`
130			`$write("error @ %t , get %d, expect %d", $time, r, a&b);`
131			`$write("\n");`
132			`end`
133			`endtask`
134
135			`task test_OR;`
136			`begin`
137			`$write(" ALU_OR \t");`
138			`a = $random % 32768;`
139			`b = $random % 32768;`
140			cmd = `ALU_OR;
141			`#10`
142			`if(r == a \| b)`
143			`$write("ok ");`
144			`else`
145			`$write("error @ %t , get %d, expect %d", $time, r, a\|b);`
146			`$write("\n");`
147			`end`
148			`endtask`
149
150			`task test_XOR;`
151			`begin`
152			`$write(" ALU_XOR \t");`
153			`a = $random % 32768;`
154			`b = $random % 32768;`
155			cmd = `ALU_XOR;
156			`#10`
157			`if(r == a ^ b)`
158			`$write("ok ");`
159			`else`
160			`$write("error @ %t , get %d, expect %d", $time, r, a^b);`
161			`$write("\n");`
162			`end`
163			`endtask`
164
165			`task test_SL;`
166			`begin`
167			`$write(" ALU_SL \t");`
168			`a = $random % 32768;`
169			`b = {$random} % 16;`
170			cmd = `ALU_SL;
171			`#10`
172			`if(r == a << b)`
173			`$write("ok ");`
174			`else`
175			`$write("error @ %t , get %d, expect %d", $time, r, a<<b);`
176			`$write("\n");`
177			`end`
178			`endtask`
179
180			`// task test_SR;`
181			`// begin`
182			`// $write(" ALU_SR \t");`
183			`// a = $random % 32768;`
184			`// b = {$random} % 16;`
185			// cmd = `ALU_SR;
186			`// #10`
187			`// if(r == a / 2**b )`
188			`// $write("ok ");`
189			`// else`
190			`// $write("error @ %t , get %d, expect %d", $time, r, (a/(2**b)));`
191			`// $write("\n");`
192			`// end`
193			`// endtask`
194			`task test_SR;`
195			`begin`
196			`$write(" ALU_SR \t");`
197			`a = 16'b1111000011110000;`
198			`b = 7;`
199			cmd = `ALU_SR;
200			`#10`
201			`if(r == 16'b1111111111100001 )`
202			`$write("ok ");`
203			`else`
204			`$write("error @ %t , get %d, expect %d", $time, r, 16'b1111111111100001);`
205			`$write("\n");`
206			`end`
207			`endtask`
208
209			`task test_SRU;`
210			`begin`
211			`$write(" ALU_SRU \t");`
212			`a = $random % 32768;`
213			`b = {$random} % 16;`
214			cmd = `ALU_SRU;
215			`#10`
216			`if(r == a >> b )`
217			`$write("ok ");`
218			`else`
219			`$write("error @ %t , get %d, expect %d", $time, r, a >> b);`
220			`$write("\n");`
221			`end`
222			`endtask`
223
224			`endmodule`
225