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[/] [mips_16/] [trunk/] [bench/] [ID_stage/] [ID_stage_tb_0.do] - Blame information for rev 2

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vlib work
vlog  +incdir+../rtl ../rtl/ID_stage.v
vlog  +incdir+../rtl ../bench/ID_stage/ID_stage_tb_0.v
 
vsim -t 1ps -novopt -lib work ID_stage_tb_0_v
view wave
add wave *
add wave /ID_stage_tb_0_v/uut/instruction_reg
view structure
view signals
run -all

Line No.	Rev	Author	Line
1	2	Doyya	`vlib work`
2			`vlog +incdir+../rtl ../rtl/ID_stage.v`
3			`vlog +incdir+../rtl ../bench/ID_stage/ID_stage_tb_0.v`
4
5			`vsim -t 1ps -novopt -lib work ID_stage_tb_0_v`
6			`view wave`
7			`add wave *`
8			`add wave /ID_stage_tb_0_v/uut/instruction_reg`
9			`view structure`
10			`view signals`
11			`run -all`

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Subversion Repositories mips_16

[/] [mips_16/] [trunk/] [bench/] [ID_stage/] [ID_stage_tb_0.do] - Blame information for rev 2