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Doyya |
/***************************************************
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* Module: ID_stage_tb_0_v
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* Project: mips_16
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* Author: fzy
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* Description:
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*
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*
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* Revise history:
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*
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***************************************************/
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`timescale 1ns/1ps
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`include "mips_16_defs.v"
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module ID_stage_tb_0_v;
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reg clk;
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reg rst;
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reg instruction_decode_en;
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// to EX_stage
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wire [56:0] pipeline_reg_out; // [56:22],35bits: ex_alu_cmd[2:0], ex_alu_src1[15:0], ex_alu_src2[15:0]
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// [21:5],17bits: mem_write_en, mem_write_data[15:0]
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// [4:0],5bits: write_back_en, write_back_dest[2:0], write_back_result_mux,
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// to IF_stage
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reg [15:0] instruction;
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wire [5:0] branch_offset_imm;
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wire branch_taken;
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// to register file
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wire [2:0] reg_read_addr_1; // register file read port 1 address
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wire [2:0] reg_read_addr_2; // register file read port 2 address
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reg [15:0] reg_read_data_1; // register file read port 1 data
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reg [15:0] reg_read_data_2; // register file read port 2 data
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// to hazard detection unit
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wire [2:0] decoding_op_src1; //source_1 register number
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wire [2:0] decoding_op_src2; //source_2 register number
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parameter CLK_PERIOD = 10;
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integer test;
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ID_stage uut(
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.clk(clk),
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.rst(rst),
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.instruction_decode_en(instruction_decode_en),
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.pipeline_reg_out(pipeline_reg_out),
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.instruction(instruction),
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.branch_offset_imm(branch_offset_imm),
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.branch_taken(branch_taken),
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.reg_read_addr_1(reg_read_addr_1), //
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.reg_read_addr_2(reg_read_addr_2), //
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.reg_read_data_1(reg_read_data_1), //
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.reg_read_data_2(reg_read_data_2), //
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.decoding_op_src1(decoding_op_src1),
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.decoding_op_src2(decoding_op_src2)
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);
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always #(CLK_PERIOD /2)
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clk =~clk;
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initial begin
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// Initialize Inputs
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clk = 0;
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rst = 0;
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instruction_decode_en = 0;
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instruction = 0;
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reg_read_data_1 = 0;
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reg_read_data_2 = 0;
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test = 0;
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// Wait 100 ns for global reset to finish
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#100;
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display_debug_message;
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#(CLK_PERIOD/2)
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test1;
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$stop;
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$finish;
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end
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task display_debug_message;
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begin
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$display("\n***************************");
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$display("ID_stage test");
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$display("***************************\n");
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end
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endtask
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task sys_reset;
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begin
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rst = 0;
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#(CLK_PERIOD*1) rst = 1;
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#(CLK_PERIOD*1) rst = 0;
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end
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endtask
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task test1;
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begin
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sys_reset;
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#1
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instruction_decode_en = 1;
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#(CLK_PERIOD) test = 1;
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#(CLK_PERIOD*100) test = 0;
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sys_reset;
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end
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endtask
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// register file behavior
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always@(*) begin
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reg_read_data_1 = 0;
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reg_read_data_2 = 0;
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if(reg_read_addr_1 == 1)
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reg_read_data_1 = 31;
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if(reg_read_addr_1 == 5)
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reg_read_data_1 = 7;
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if(reg_read_addr_1 == 7)
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reg_read_data_1 = 0;// ==0, BZ will taken
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// reg_read_data_1 = 3; // !=0, BZ will not taken
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if(reg_read_addr_2 == 2)
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reg_read_data_2 = 28;
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if(reg_read_addr_2 == 4)
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reg_read_data_2 = 16'h9a3c;
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if(reg_read_addr_2 == 6)
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reg_read_data_2 = 16'hc32e;
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end
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always @ (test) begin
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case(test)
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1: begin
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$display("running test1\n");
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$display("check datapath control logic S1~S6 correct or not\n");
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//while(test == 1) begin
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// NOP
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#(CLK_PERIOD) instruction = { `OP_NOP, 12'b0};
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$display("OP_NOP\n");
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// ADD
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#(CLK_PERIOD) instruction = { `OP_ADD, 3'd0, 3'd1, 3'd2, 3'd0};
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$display("OP_ADD\n");
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#(CLK_PERIOD)
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if(
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uut.write_back_en != 1 || // S3
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uut.write_back_result_mux != 0 || // S1
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uut.ex_alu_cmd != `ALU_ADD || // S2
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uut.alu_src2_mux != 0 || // S4
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uut.decoding_op_is_branch != 0 || // S5
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uut.decoding_op_is_store != 0 || // S6
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decoding_op_src1 != 1 ||
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decoding_op_src2 != 2 ||
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branch_taken != 0 ||
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branch_offset_imm != 6'b010000||
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reg_read_addr_1 != 1 ||
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reg_read_addr_2 != 2
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)
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$display("error1\n");
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#(CLK_PERIOD)
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if(
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pipeline_reg_out[56:54] != `ALU_ADD || // S2 ex_alu_cmd
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pipeline_reg_out[53:38] != 31 || // alu src1
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pipeline_reg_out[37:22] != 28 || // alu src2
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pipeline_reg_out[21] != 0 || // mem_write_en
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pipeline_reg_out[20:5] != 28 || // mem_write_data
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pipeline_reg_out[4] != 1 || // S3 write_back_en
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pipeline_reg_out[3:1] != 0 || // write_back_dest
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pipeline_reg_out[0] != 0 // S1 write_back_result_mux
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)
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$display("error2\n");
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// ST
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#(CLK_PERIOD) instruction = { `OP_ST, 3'd4, 3'd5, 6'd31};
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$display("OP_ST\n");
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#(CLK_PERIOD)
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if(
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uut.write_back_en != 0 || // S3
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uut.write_back_result_mux != 1'bx || // S1
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uut.ex_alu_cmd != `ALU_ADD || // S2
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uut.alu_src2_mux != 1 || // S4
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uut.decoding_op_is_branch != 0 || // S5
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uut.decoding_op_is_store != 1 || // S6
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decoding_op_src1 != 5 ||
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decoding_op_src2 != 4 ||
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branch_taken != 0 ||
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branch_offset_imm != 6'd31 ||
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reg_read_addr_1 != 5 ||
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reg_read_addr_2 != 4
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)
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$display("error1\n");
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#(CLK_PERIOD)
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if(
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pipeline_reg_out[53:38] != 7 || // ex_alu_src1
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pipeline_reg_out[37:22] != 31 || // ex_alu_src2
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pipeline_reg_out[21] != 1 || // mem_write_en
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pipeline_reg_out[20:5] != 16'h9a3c || // mem_write_data
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pipeline_reg_out[3:1] != 4 // write_back_dest
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)
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$display("error2\n");
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// BZ
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#(CLK_PERIOD) instruction = { `OP_BZ, 3'd0, 3'd7, -6'd10};
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$display("OP_BZ\n");
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#(CLK_PERIOD)
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if(
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uut.write_back_en != 0 || // S3
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uut.write_back_result_mux != 1'bx || // S1
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uut.ex_alu_cmd != `ALU_NC || // S2
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uut.alu_src2_mux != 1 || // S4
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uut.decoding_op_is_branch != 1 || // S5
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uut.decoding_op_is_store != 0 || // S6
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decoding_op_src1 != 7 ||
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decoding_op_src2 != 0 ||
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branch_taken != 1 ||
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// branch_taken != 0 ||
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branch_offset_imm != -6'd10 ||
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reg_read_addr_1 != 7 ||
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reg_read_addr_2 != 3'b110
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)
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$display("error1\n");
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#(CLK_PERIOD)
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if(
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pipeline_reg_out[53:38] != 0 || // ex_alu_src1
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// pipeline_reg_out[53:38] != 3 || // ex_alu_src1
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pipeline_reg_out[37:22] != -6'd10 || // ex_alu_src2
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pipeline_reg_out[21] != 0 || // mem_write_en
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pipeline_reg_out[20:5] != 16'hc32e || // mem_write_data
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pipeline_reg_out[3:1] != 0 // write_back_dest
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)
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$display("error2\n");
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//end
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end
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endcase
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end
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endmodule
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