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[/] [mips_16/] [trunk/] [bench/] [IF_stage/] [IF_stage_tb_0.do] - Blame information for rev 2

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vlib work
##vlog  +incdir+F:/Projects/My_MIPS/mips_16/rtl ../rtl/*.v
vlog  +incdir+../rtl ../rtl/IF_stage.v
vlog  +incdir+../rtl ../rtl/instruction_mem.v
vlog  +incdir+../rtl ../bench/IF_stage/IF_stage_tb_0.v
 
vsim -t 1ps -novopt -L xilinxcorelib_ver -L unisims_ver -lib work IF_stage_tb_0_v
view wave
add wave *
## add wave /glbl/GSR
## do {dds_tb_v.udo}
view structure
view signals
run -all

Line No.	Rev	Author	Line
1	2	Doyya	`vlib work`
2			`##vlog +incdir+F:/Projects/My_MIPS/mips_16/rtl ../rtl/*.v`
3			`vlog +incdir+../rtl ../rtl/IF_stage.v`
4			`vlog +incdir+../rtl ../rtl/instruction_mem.v`
5			`vlog +incdir+../rtl ../bench/IF_stage/IF_stage_tb_0.v`
6
7			`vsim -t 1ps -novopt -L xilinxcorelib_ver -L unisims_ver -lib work IF_stage_tb_0_v`
8			`view wave`
9			`add wave *`
10			`## add wave /glbl/GSR`
11			`## do {dds_tb_v.udo}`
12			`view structure`
13			`view signals`
14			`run -all`

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Subversion Repositories mips_16

[/] [mips_16/] [trunk/] [bench/] [IF_stage/] [IF_stage_tb_0.do] - Blame information for rev 2