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[/] [mips_16/] [trunk/] [bench/] [mips_16_core_top/] [mips_16_core_top_tb_0.do] - Blame information for rev 2

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Line No. Rev Author Line
1 2 Doyya
quit -sim
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vlib work
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vlog  +incdir+../rtl ../rtl/*.v
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vlog  +incdir+../rtl ../bench/mips_16_core_top/mips_16_core_top_tb_0.v
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vsim -t 1ps -novopt -lib work mips_16_core_top_tb_0_v
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view wave
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#add wave *
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add wave /mips_16_core_top_tb_0_v/uut/*
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add wave -radix unsigned /mips_16_core_top_tb_0_v/uut/ID_stage_inst/ir_op_code
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add wave -radix unsigned /mips_16_core_top_tb_0_v/uut/ID_stage_inst/ir_dest
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add wave -radix unsigned /mips_16_core_top_tb_0_v/uut/ID_stage_inst/ir_src1
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add wave -radix unsigned /mips_16_core_top_tb_0_v/uut/ID_stage_inst/ir_src2
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add wave -radix unsigned /mips_16_core_top_tb_0_v/uut/ID_stage_inst/ir_imm
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view structure
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view signals
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run -all

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