URL https://opencores.org/ocsvn/mips_16/mips_16/trunk

Subversion Repositories mips_16

[/] [mips_16/] [trunk/] [bench/] [mips_16_core_top/] [mips_16_core_top_tb_0.do] - Blame information for rev 2

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quit -sim
vlib work
vlog  +incdir+../rtl ../rtl/*.v
vlog  +incdir+../rtl ../bench/mips_16_core_top/mips_16_core_top_tb_0.v
 
vsim -t 1ps -novopt -lib work mips_16_core_top_tb_0_v
view wave
#add wave *
add wave /mips_16_core_top_tb_0_v/uut/*
add wave -radix unsigned /mips_16_core_top_tb_0_v/uut/ID_stage_inst/ir_op_code
add wave -radix unsigned /mips_16_core_top_tb_0_v/uut/ID_stage_inst/ir_dest
add wave -radix unsigned /mips_16_core_top_tb_0_v/uut/ID_stage_inst/ir_src1
add wave -radix unsigned /mips_16_core_top_tb_0_v/uut/ID_stage_inst/ir_src2
add wave -radix unsigned /mips_16_core_top_tb_0_v/uut/ID_stage_inst/ir_imm
 
view structure
view signals
run -all

Line No.	Rev	Author	Line
1	2	Doyya	`quit -sim`
2			`vlib work`
3			`vlog +incdir+../rtl ../rtl/*.v`
4			`vlog +incdir+../rtl ../bench/mips_16_core_top/mips_16_core_top_tb_0.v`
5
6			`vsim -t 1ps -novopt -lib work mips_16_core_top_tb_0_v`
7			`view wave`
8			`#add wave *`
9			`add wave /mips_16_core_top_tb_0_v/uut/*`
10			`add wave -radix unsigned /mips_16_core_top_tb_0_v/uut/ID_stage_inst/ir_op_code`
11			`add wave -radix unsigned /mips_16_core_top_tb_0_v/uut/ID_stage_inst/ir_dest`
12			`add wave -radix unsigned /mips_16_core_top_tb_0_v/uut/ID_stage_inst/ir_src1`
13			`add wave -radix unsigned /mips_16_core_top_tb_0_v/uut/ID_stage_inst/ir_src2`
14			`add wave -radix unsigned /mips_16_core_top_tb_0_v/uut/ID_stage_inst/ir_imm`
15
16			`view structure`
17			`view signals`
18			`run -all`

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Subversion Repositories mips_16

[/] [mips_16/] [trunk/] [bench/] [mips_16_core_top/] [mips_16_core_top_tb_0.do] - Blame information for rev 2