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[/] [mips_16/] [trunk/] [bench/] [mips_16_core_top/] [mips_16_core_top_tb_0.v] - Blame information for rev 2

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Line No. Rev Author Line
1 2 Doyya
////////////////////////////////////////////////////////////////////////////////
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// Company: 
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// Engineer:
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//
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// Create Date:   19:38:28 02/09/2012
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// Design Name:   mips_16_core_top
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// Module Name:   F:/Projects/My_MIPS/mips_16/bench/mips_16_core_top/mips_16_core_top_tb_0.v
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// Project Name:  mips_16
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// Target Device:  
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// Tool versions:  
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// Description: 
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//
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// Verilog Test Fixture created by ISE for module: mips_16_core_top
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//
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// Dependencies:
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// 
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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// 
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////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns/1ps
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`include "mips_16_defs.v"
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module mips_16_core_top_tb_0_v;
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        // Inputs
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        reg clk;
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        reg rst;
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        // Outputs
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        wire [`PC_WIDTH-1:0] pc;
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        parameter CLK_PERIOD = 10;
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        always #(CLK_PERIOD /2)
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                clk =~clk;
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        integer i;
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        integer test;
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        // Instantiate the Unit Under Test (UUT)
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        mips_16_core_top uut (
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                .clk(clk),
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                .rst(rst),
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                .pc(pc)
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        );
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        initial begin
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                // Initialize Inputs
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                clk = 0;
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                rst = 0;
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                // Wait 100 ns for global reset to finish
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                #100;
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                // Add stimulus here
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                #(CLK_PERIOD/2)
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                #1
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                display_debug_message;
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                //test1;
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                test2;
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                $stop;
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        end
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        task display_debug_message;
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                begin
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                        $display("\n***************************");
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                        $display("mips_16 core test");
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                        $display("***************************\n");
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                end
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        endtask
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        task sys_reset;
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                begin
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                        rst = 0;
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                        #(CLK_PERIOD*1) rst = 1;
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                        #(CLK_PERIOD*1) rst = 0;
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                end
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        endtask
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        task test1;
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                begin
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                        $readmemb("../bench/mips_16_core_top/test1.prog",uut.IF_stage_inst.imem.rom);
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                        $display("rom load successfully\n");
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                        $display("running test1\n");
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                        sys_reset;
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                        #1
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                        //#(CLK_PERIOD) test = 1;
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                        $monitor("current pc: %d ,instruction: %x", pc, uut.instruction);
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                        #(CLK_PERIOD*100)
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                        $monitoroff;
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                        display_all_regs;
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                        $display("ram[10] = %d", uut.MEM_stage_inst.dmem.ram[10]);
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                        //#(CLK_PERIOD*100) test = 0;
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                        sys_reset;
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                end
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        endtask
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        task test2;
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                begin
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                        $readmemb("../bench/mips_16_core_top/test2.prog",uut.IF_stage_inst.imem.rom);
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                        $display("rom load successfully\n");
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                        $display("running test2\n");
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                        $display("multiply R3=R1*R2\n");
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                        sys_reset;
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                        display_all_regs;
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                        #1
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                        test = 2;
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                        //#(CLK_PERIOD) test = 1;
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                        $monitor("current pc: %d ,instruction: %x", pc, uut.instruction);
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                        #(CLK_PERIOD*400)
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                        $monitoroff;
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                        display_all_regs;
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                        test = 0;
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                        sys_reset;
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                end
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        endtask
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        task display_all_regs;
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                begin
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                        $display("display_all_regs:");
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                        $display("------------------------------");
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                        $display("R0\tR1\tR2\tR3\tR4\tR5\tR6\tR7");
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                        for(i=0; i<8; i=i+1)
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                                        $write("%d\t",uut.register_file_inst.reg_array[i]);
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                        $display("\n------------------------------");
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                end
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        endtask
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        always @ (test) begin
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            case(test)
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                        // 1: begin
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                            // $display("running test1\n");
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                                 // while(test == 1) begin
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                                    // @(uut.pc)
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                                        // $display("current pc : %d",uut.pc);
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                                        // if(uut.pc == 40) begin
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                                                // #1
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                                            // branch_taken = 1;
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                                                // branch_offset_imm = -30;
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                                                // #(CLK_PERIOD*1) 
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                                                // branch_taken =0;
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                                                // branch_offset_imm = 0;
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                                        // end
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                                 // end
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                        // end
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                        2: begin
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                            $display("running test2\n");
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                                 while(test == 2) begin
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                                    @(pc)
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                                        if(pc==6) begin
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                                                $display("current pc : %d",uut.pc);
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                                                display_all_regs();
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                                        end
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                                 end
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                        end
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                endcase
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        end
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endmodule
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