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[/] [mips_16/] [trunk/] [bench/] [register_file/] [register_file_tb_0.v] - Blame information for rev 2

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Line No. Rev Author Line
1 2 Doyya
 
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////////////////////////////////////////////////////////////////////////////////
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// Company: 
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// Engineer:
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//
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// Create Date:   15:38:17 02/08/2012
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// Design Name:   register_file
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// Module Name:   F:/Projects/My_MIPS/mips_16/bench/register_file/register_file_tb_0.v
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// Project Name:  mips_16
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// Target Device:  
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// Tool versions:  
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// Description: 
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//
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// Verilog Test Fixture created by ISE for module: register_file
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//
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// Dependencies:
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// 
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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// 
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////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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`include "mips_16_defs.v"
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module register_file_tb_0_v;
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        // Inputs
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        reg clk;
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        reg rst;
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        reg reg_write_en;
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        reg [2:0] reg_write_dest;
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        reg [15:0] reg_write_data;
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        reg [2:0] reg_read_addr_1;
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        reg [2:0] reg_read_addr_2;
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        // Outputs
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        wire [15:0] reg_read_data_1;
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        wire [15:0] reg_read_data_2;
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        // Instantiate the Unit Under Test (UUT)
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        register_file uut (
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                .clk(clk),
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                .rst(rst),
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                .reg_write_en(reg_write_en),
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                .reg_write_dest(reg_write_dest),
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                .reg_write_data(reg_write_data),
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                .reg_read_addr_1(reg_read_addr_1),
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                .reg_read_data_1(reg_read_data_1),
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                .reg_read_addr_2(reg_read_addr_2),
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                .reg_read_data_2(reg_read_data_2)
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        );
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        parameter CLK_PERIOD = 10;
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        always #(CLK_PERIOD /2)
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                clk =~clk;
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        integer i;
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        reg [15:0] rand;
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        initial begin
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                // Initialize Inputs
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                clk = 0;
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                rst = 0;
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                reg_write_en = 0;
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                reg_write_dest = 0;
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                reg_write_data = 0;
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                reg_read_addr_1 = 0;
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                reg_read_addr_2 = 0;
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                // Wait 100 ns for global reset to finish
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                #100;
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                // Add stimulus here
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                #(CLK_PERIOD/2)
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                #1
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                #(CLK_PERIOD*1) rst = 1;
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                #(CLK_PERIOD*1) rst = 0;
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                #(CLK_PERIOD*10)
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                display_all_regs;
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                write_all_regs;
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                read_all_regs_from_read_port_1;
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                read_all_regs_from_read_port_2;
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                write_and_read_all_regs;
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                $stop;
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                $finish;
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        end
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        task display_all_regs;
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                begin
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                        $display("display_all_regs:");
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                        $display("------------------------------");
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                        $display("R0\tR1\tR2\tR3\tR4\tR5\tR6\tR7");
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                        for(i=0; i<8; i=i+1)
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                                        $write("%d\t",uut.reg_array[i]);
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                        $display("\n------------------------------");
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                end
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        endtask
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        task read_all_regs_from_read_port_1;
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                begin
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                        $display("read_all_regs_from_read_port_1:");
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                        $display("------------------------------");
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                        $display("R0\tR1\tR2\tR3\tR4\tR5\tR6\tR7");
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                        i=0;
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                        while(i<8) begin
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                                reg_read_addr_1 = i;
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                                #(CLK_PERIOD*1)
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                                $write("%d\t",reg_read_data_1);
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                                i=i+1;
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                        end
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                        $display("\n------------------------------");
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                end
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        endtask
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        task read_all_regs_from_read_port_2;
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                begin
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                        $display("read_all_regs_from_read_port_2:");
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                        $display("------------------------------");
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                        $display("R0\tR1\tR2\tR3\tR4\tR5\tR6\tR7");
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                        i=0;
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                        while(i<8) begin
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                                reg_read_addr_2 = i;
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                                #(CLK_PERIOD*1)
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                                $write("%d\t",reg_read_data_2);
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                                i=i+1;
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                        end
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                        $display("\n------------------------------");
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                end
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        endtask
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        task write_all_regs;
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                begin
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                        $display("write_all_regs(random):");
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                        $display("------------------------------");
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                        $display("R0\tR1\tR2\tR3\tR4\tR5\tR6\tR7");
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                        i=0;
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                        while(i<8) begin
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                                reg_write_en=1;
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                                reg_write_dest = i;
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                                reg_write_data = $random % 32768;
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                                #(CLK_PERIOD*1)
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                                $write("%d\t",uut.reg_array[i]);
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                                reg_write_en=0;
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                                i=i+1;
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                        end
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                        $display("\n------------------------------");
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                end
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        endtask
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        reg [15:0] read_tmp_1[7:0];
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        reg [15:0] read_tmp_2[7:0];
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        task write_and_read_all_regs;
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                begin
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                        $display("write_and_read_all_regs(random):");
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                        $display("------------------------------");
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                        $display("R0\tR1\tR2\tR3\tR4\tR5\tR6\tR7");
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                        $display("newly wrote values:");
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                        $display("------------------------------");
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                        i=0;
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                        while(i<8) begin
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                                reg_write_en=1;
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                                reg_write_dest = i;
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                                reg_write_data = $random % 32768;
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                                reg_read_addr_1 = i;
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                                reg_read_addr_2 = i-1;
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                                #(CLK_PERIOD*0.5)
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                                read_tmp_1[i]=reg_read_data_1;
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                                if(reg_read_data_1 > 0)
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                                        read_tmp_2[i-1]=reg_read_data_2;
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                                #(CLK_PERIOD*0.5)
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                                $write("%d\t",uut.reg_array[i]);
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                                reg_write_en=0;
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                                i=i+1;
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                        end
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                        reg_read_addr_2 = i-1;
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                        #(CLK_PERIOD*0.5)
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                        read_tmp_2[i-1]=reg_read_data_2;
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                        #(CLK_PERIOD*0.5)
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                        $display("\n------------------------------");
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                        $display("read from port 1 (read regs being wrote will hold its value):");
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                        $display("------------------------------");
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                        i=0;
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                        while(i<8) begin
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                                $write("%d\t",read_tmp_1[i]);
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                                i=i+1;
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                        end
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                        $display("\n------------------------------");
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                        $display("read from port 2 (read wrote regs will get its new value):");
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                        $display("------------------------------");
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                        i=0;
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                        while(i<8) begin
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                                $write("%d\t",read_tmp_2[i]);
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                                i=i+1;
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                        end
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                        $display("\n------------------------------");
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                end
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        endtask
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endmodule
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