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Doyya |
/***************************************************
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* Module: ID_stage
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* Project: mips_16
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* Author: fzy
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* Description:
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* IR, and instruction decoding
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*
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* Revise history:
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*
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***************************************************/
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`timescale 1ns/1ps
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`include "mips_16_defs.v"
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module ID_stage
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(
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input clk,
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input rst,
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input instruction_decode_en,
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//input insert_bubble,
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// to EX_stage
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output reg [56:0] pipeline_reg_out, // [56:22],35bits: ex_alu_cmd[2:0], ex_alu_src1[15:0], ex_alu_src2[15:0]
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// [21:5],17bits: mem_write_en, mem_write_data[15:0]
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// [4:0],5bits: write_back_en, write_back_dest[2:0], write_back_result_mux,
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// to IF_stage
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input [15:0] instruction,
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output [5:0] branch_offset_imm,
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output reg branch_taken,
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// to register file
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output [2:0] reg_read_addr_1, // register file read port 1 address
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output [2:0] reg_read_addr_2, // register file read port 2 address
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input [15:0] reg_read_data_1, // register file read port 1 data
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input [15:0] reg_read_data_2, // register file read port 2 data
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// to hazard detection unit
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output [2:0] decoding_op_src1, //source_1 register number
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output [2:0] decoding_op_src2 //source_2 register number
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);
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/********************** internal wires ***********************************/
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//----------------- Instruction Register signals --------------------//
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reg [15:0] instruction_reg;
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wire [3:0] ir_op_code; //operation code
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wire [2:0] ir_dest; //destination register number
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wire [2:0] ir_src1; //source_1 register number
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wire [2:0] ir_src2; //source_2 register number
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wire [5:0] ir_imm; //immediate number carried by the instruction
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//---------------- data path control signals --------------------------//
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// write back stage signals
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reg write_back_en; // S3
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wire [2:0] write_back_dest; // dest
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reg write_back_result_mux; // S1
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// mem stage signals
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wire mem_write_en;
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wire [15:0] mem_write_data;
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// ex stage signals
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reg [2:0] ex_alu_cmd; //S2
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wire [15:0] ex_alu_src1;
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wire [15:0] ex_alu_src2;
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// instruction decode stage signals
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reg alu_src2_mux; // S4
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wire decoding_op_is_branch; //S5
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wire decoding_op_is_store; //S6
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wire [3:0] ir_op_code_with_bubble;
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wire [2:0] ir_dest_with_bubble;
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//reg branch_condition_satisfied;
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/********************** Instruction Register *********************/
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always @ (posedge clk or posedge rst) begin
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if(rst) begin
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instruction_reg <= 0;
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end
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else begin
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if(instruction_decode_en) begin
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instruction_reg <= instruction;
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end
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end
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end
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assign ir_op_code = instruction_reg[15:12];
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assign ir_dest = instruction_reg[11: 9];
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assign ir_src1 = instruction_reg[ 8: 6];
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assign ir_src2 = (decoding_op_is_store)? instruction_reg[11: 9] : instruction_reg[ 5: 3];
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assign ir_imm = instruction_reg[ 5: 0];
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/********************** pipeline bubble insertion *********************/
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// if instrcution decode is frozen, insert bubble operations into the pipeline
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assign ir_op_code_with_bubble = ( instruction_decode_en )? ir_op_code : 0;
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// if instrcution decode is frozen, force destination reg number to 0,
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// this operation is to prevent pipeline stall.
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assign ir_dest_with_bubble = ( instruction_decode_en )? ir_dest : 0;
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/********************** Data path control logic *********************/
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always @ (*) begin
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if(rst) begin
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write_back_en = 0; // S3
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write_back_result_mux = 0; // S1
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ex_alu_cmd = 0; // S2
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alu_src2_mux = 0; // S4
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end
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else begin
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case( ir_op_code_with_bubble )
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`OP_NOP :
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begin
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write_back_en = 0; // S3
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write_back_result_mux = 1'bx; // S1
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ex_alu_cmd = `ALU_NC; // S2
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alu_src2_mux = 1'bx; // S4
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end
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`OP_ADD :
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begin
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write_back_en = 1; // S3
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write_back_result_mux = 0; // S1
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ex_alu_cmd = `ALU_ADD; // S2
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alu_src2_mux = 0; // S4
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end
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`OP_SUB :
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begin
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write_back_en = 1; // S3
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write_back_result_mux = 0; // S1
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ex_alu_cmd = `ALU_SUB; // S2
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alu_src2_mux = 0; // S4
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end
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`OP_AND :
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begin
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write_back_en = 1; // S3
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write_back_result_mux = 0; // S1
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ex_alu_cmd = `ALU_AND; // S2
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alu_src2_mux = 0; // S4
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end
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`OP_OR :
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begin
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write_back_en = 1; // S3
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write_back_result_mux = 0; // S1
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ex_alu_cmd = `ALU_OR; // S2
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alu_src2_mux = 0; // S4
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end
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`OP_XOR :
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begin
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write_back_en = 1; // S3
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write_back_result_mux = 0; // S1
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ex_alu_cmd = `ALU_XOR; // S2
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alu_src2_mux = 1'bx; // S4
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end
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`OP_SL :
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begin
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write_back_en = 1; // S3
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write_back_result_mux = 0; // S1
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ex_alu_cmd = `ALU_SL; // S2
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alu_src2_mux = 0; // S4
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end
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`OP_SR :
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begin
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write_back_en = 1; // S3
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write_back_result_mux = 0; // S1
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ex_alu_cmd = `ALU_SR; // S2
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alu_src2_mux = 0; // S4
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end
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`OP_SRU :
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begin
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write_back_en = 1; // S3
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write_back_result_mux = 0; // S1
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ex_alu_cmd = `ALU_SRU; // S2
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alu_src2_mux = 0; // S4
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end
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`OP_ADDI:
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begin
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write_back_en = 1; // S3
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write_back_result_mux = 0; // S1
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ex_alu_cmd = `ALU_ADD; // S2
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alu_src2_mux = 1; // S4
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end
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`OP_LD :
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begin
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write_back_en = 1; // S3
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write_back_result_mux = 1; // S1
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ex_alu_cmd = `ALU_ADD; // S2
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alu_src2_mux = 1; // S4
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end
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`OP_ST :
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begin
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write_back_en = 0; // S3
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write_back_result_mux = 1'bx; // S1
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ex_alu_cmd = `ALU_ADD; // S2
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alu_src2_mux = 1; // S4
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end
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`OP_BZ :
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begin
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write_back_en = 0; // S3
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write_back_result_mux = 1'bx; // S1
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ex_alu_cmd = `ALU_NC; // S2
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alu_src2_mux = 1; // S4
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end
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default :
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begin
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write_back_en = 0; // S3
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write_back_result_mux = 1'bx; // S1
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ex_alu_cmd = `ALU_NC; // S2
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alu_src2_mux = 1'bx; // S4
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`ifndef CODE_FOR_SYNTHESIS
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$display("ERROR: Unknown Instruction: %b", ir_op_code_with_bubble);
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//$stop;
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`endif
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end
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endcase
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end
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end
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assign decoding_op_is_branch = ( ir_op_code == `OP_BZ )? 1 : 0; // S5
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assign decoding_op_is_store = ( ir_op_code == `OP_ST )? 1 : 0; // S6
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/********************** singals to EX_stage *********************/
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assign mem_write_data = reg_read_data_2;
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assign mem_write_en = decoding_op_is_store;
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assign write_back_dest = ir_dest_with_bubble;
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assign ex_alu_src1 = reg_read_data_1;
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assign ex_alu_src2 = (alu_src2_mux)? {{10{ir_imm[5]}},ir_imm} : reg_read_data_2;
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// pipeline_reg_out:
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// [56:22],35bits: ex_alu_cmd[2:0], ex_alu_src1[15:0], ex_alu_src2[15:0],
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// [21:5],17bits: mem_write_en, mem_write_data[15:0],
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// [4:0],5bits: write_back_en, write_back_dest[2:0], write_back_result_mux,
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always @ (posedge clk or posedge rst) begin
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if(rst) begin
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pipeline_reg_out[56:0] <= 0;
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end
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else begin
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pipeline_reg_out[56:0] <= {
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ex_alu_cmd[2:0], // pipeline_reg_out[56:54] //S2
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ex_alu_src1[15:0], // pipeline_reg_out[53:38]
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ex_alu_src2[15:0], // pipeline_reg_out[37:22]
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mem_write_en, // pipeline_reg_out[21] //
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mem_write_data[15:0], // pipeline_reg_out[20:5] //
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write_back_en, // pipeline_reg_out[4] //S3
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write_back_dest[2:0], // pipeline_reg_out[3:1] //dest
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write_back_result_mux // pipeline_reg_out[0] //S1
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};
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end
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end
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/********************** interface with register file *********************/
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assign reg_read_addr_1 = ir_src1;
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assign reg_read_addr_2 = ir_src2;
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/********************** branch signals generate *********************/
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always @ (*) begin
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if(decoding_op_is_branch) begin
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case( ir_dest_with_bubble )
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`BRANCH_Z :
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begin
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if(reg_read_data_1 == 0)
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branch_taken = 1;
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else
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branch_taken = 0;
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end
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default:
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begin
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branch_taken = 0;
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`ifndef CODE_FOR_SYNTHESIS
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$display("ERROR: Unknown branch condition %b, in branch instruction %b \n", ir_dest_with_bubble, ir_op_code_with_bubble);
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//$stop;
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`endif
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end
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endcase
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end
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else begin
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branch_taken = 0;
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end
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end
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assign branch_offset_imm = ir_imm;
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//assign branch_taken = decoding_op_is_branch & branch_condition_satisfied ;
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/********************** to hazard detection unit *********************/
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assign decoding_op_src1 = ir_src1;
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assign decoding_op_src2 = (
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ir_op_code == `OP_NOP ||
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ir_op_code == `OP_ADDI ||
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ir_op_code == `OP_LD ||
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ir_op_code == `OP_BZ
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)?
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3'b000 : ir_src2;
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endmodule
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