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[/] [mips_16/] [trunk/] [rtl/] [IF_stage.v] - Blame information for rev 4

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/***************************************************
 * Module: IF_stage
 * Project: mips_16
 * Author: fzy
 * Description:
 *     PC, IMEM,
 *
 * Revise history:
 *
 ***************************************************/
`timescale 1ns/1ps
`include "mips_16_defs.v"
 
 
module IF_stage
(
        input                                                   clk,
        input                                                   rst,                            //active high
        input                                                   instruction_fetch_en,
 
        input   [5:0]                                    branch_offset_imm,
        input                                                   branch_taken,
 
        output  reg     [`PC_WIDTH-1:0]          pc,
        output  [15:0]                                   instruction
);
 
        // pc control
        always @ (posedge clk or posedge rst) begin
            if (rst) begin
                pc <= `PC_WIDTH'b0;
            end
                else begin
                        if(instruction_fetch_en) begin
                                if(branch_taken)
                                        //don't forget sign bit expansion
                                        pc <= pc + {{(`PC_WIDTH-6){branch_offset_imm[5]}}, branch_offset_imm[5:0]};
                                else
                                        pc <= pc + `PC_WIDTH'd1;
                        end
                end
        end
 
        // instruction memory, or rom
        instruction_mem imem(
                .clk                            (clk),
                .pc                                     (pc),
 
                .instruction            (instruction)
        );
 
 
endmodule
 
 
 

Line No.	Rev	Author	Line
1	4	Doyya	`/***************************************************`
2			`* Module: IF_stage`
3			`* Project: mips_16`
4			`* Author: fzy`
5			`* Description:`
6			`* PC, IMEM,`
7			`*`
8			`* Revise history:`
9			`*`
10			`***************************************************/`
11			`timescale 1ns/1ps
12			`include "mips_16_defs.v"
13
14
15			`module IF_stage`
16			`(`
17			`input clk,`
18			`input rst, //active high`
19			`input instruction_fetch_en,`
20
21			`input [5:0] branch_offset_imm,`
22			`input branch_taken,`
23
24			output reg [`PC_WIDTH-1:0] pc,
25			`output [15:0] instruction`
26			`);`
27
28			`// pc control`
29			`always @ (posedge clk or posedge rst) begin`
30			`if (rst) begin`
31			pc <= `PC_WIDTH'b0;
32			`end`
33			`else begin`
34			`if(instruction_fetch_en) begin`
35			`if(branch_taken)`
36			`//don't forget sign bit expansion`
37			pc <= pc + {{(`PC_WIDTH-6){branch_offset_imm[5]}}, branch_offset_imm[5:0]};
38			`else`
39			pc <= pc + `PC_WIDTH'd1;
40			`end`
41			`end`
42			`end`
43
44			`// instruction memory, or rom`
45			`instruction_mem imem(`
46			`.clk (clk),`
47			`.pc (pc),`
48
49			`.instruction (instruction)`
50			`);`
51
52
53			`endmodule`
54
55
56

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[/] [mips_16/] [trunk/] [rtl/] [IF_stage.v] - Blame information for rev 4