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[/] [mips_16/] [trunk/] [rtl/] [hazard_detection_unit.v] - Blame information for rev 4

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1 4 Doyya 
/***************************************************
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 * Module: hazard_detection_unit
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 * Project: mips_16
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 * Author: fzy
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 * Description:
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 *    Data Hazard detection. if there is a RAW hazard, it will stall the pipeline.
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 *
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 *       *       Method: It compare the source register of the instruction in ID_stage
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 *                       and it's previous 3 instructions' destination register. If
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 *                       the source register is equal to any of the three destination regs
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 *                       and not equals to zero, the Hazard Detction Unit will assert
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 *                       pipeline_stall signal. That signal will freeze the IF & ID stage,
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 *                       and insert bubbles into EX stage. When the hazard instruction
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 *                       was flushed out of the pipeline, pipeline_stall signal will
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 *                       be canceled.
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 *
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 * Revise history:
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 *
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 ***************************************************/
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module hazard_detection_unit
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(
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        input           [2:0]            decoding_op_src1,               //ID stage source_1 register number
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        input           [2:0]            decoding_op_src2,               //ID stage source_2 register number
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        input           [2:0]            ex_op_dest,                             //EX stage destinaton register number
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        input           [2:0]            mem_op_dest,                    //MEM stage destinaton register number
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        input           [2:0]            wb_op_dest,                             //WB stage destinaton register number
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        output  reg                             pipeline_stall_n                // Active low
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);
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        always @ (*) begin
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                pipeline_stall_n = 1;
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                if( decoding_op_src1 != 0 &&
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                        (
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                                decoding_op_src1 == ex_op_dest  ||
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                                decoding_op_src1 == mem_op_dest ||
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                                decoding_op_src1 == wb_op_dest
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                        )
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                )
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                        pipeline_stall_n = 0;
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                if( decoding_op_src2 != 0 &&
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                        (
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                                decoding_op_src2 == ex_op_dest  ||
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                                decoding_op_src2 == mem_op_dest ||
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                                decoding_op_src2 == wb_op_dest
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                        )
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                )
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                        pipeline_stall_n = 0;
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        end
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endmodule

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