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[/] [mips_16/] [trunk/] [rtl/] [instruction_mem.v] - Blame information for rev 4

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1 4 Doyya 
/***************************************************
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 * Module: instruction_mem
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 * Project: mips_16
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 * Author: fzy
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 * Description:
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 *     a rom
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 *
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 * Revise history:
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 *
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 ***************************************************/
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`timescale 1ns/1ps
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`include "mips_16_defs.v"
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`ifdef USE_SIMULATION_CODE
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module instruction_mem          // a rtl simulation rom, rom initial code can be found in the testbench
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(
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        input                                   clk,            // asynchronized!!
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        input   [`PC_WIDTH-1:0]  pc,
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        output  [15:0]                   instruction
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);
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        reg     [15:0] rom [2**`INSTR_MEM_ADDR_WIDTH-1 : 0];
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        wire [`INSTR_MEM_ADDR_WIDTH-1 : 0] rom_addr = pc[`INSTR_MEM_ADDR_WIDTH-1 : 0];
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        // always @ (posedge clk) begin
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        // always @ (*) begin
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            // instruction = rom[rom_addr];
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        // end
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        assign instruction = rom[rom_addr];
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endmodule
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`endif
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`ifndef USE_SIMULATION_CODE
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module instruction_mem          // a synthesisable rom implementation
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(
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        input                                   clk,            // asynchronized!!
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        input   [`PC_WIDTH-1:0]  pc,
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        output reg      [15:0]           instruction
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);
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        wire [`INSTR_MEM_ADDR_WIDTH-1 : 0] rom_addr = pc[`INSTR_MEM_ADDR_WIDTH-1 : 0];
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        // ASM code in rom:
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        // L1:  ADDI            R1,R0,8
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        //              ADDI            R2,R1,8
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        //              ADDI            R3,R2,8
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        //              ADD                     R4,R2,R3
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        //              ST                      R4,R1,2
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        //              LD                      R5,R1,2
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        //              SUB                     R6,R4,R5
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        //              BZ                      R6,L1
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        //              ADDI            R7,R7,1
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        always @(*)
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                case (rom_addr)
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                        4'b0000: instruction = 16'b1001001000001000;
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                        4'b0001: instruction = 16'b1001010001001000;
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                        4'b0010: instruction = 16'b1001011010001000;
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                        4'b0011: instruction = 16'b0001100010011000;
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                        4'b0100: instruction = 16'b1011100001000010;
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                        4'b0101: instruction = 16'b1010101001000010;
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                        4'b0110: instruction = 16'b0010110100101000;
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                        4'b0111: instruction = 16'b1100000110111000;
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                        4'b1000: instruction = 16'b1001111111000001;
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                        4'b1001: instruction = 16'b0000000000000000;
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                        4'b1010: instruction = 16'b0000000000000000;
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                        4'b1011: instruction = 16'b0000000000000000;
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                        4'b1100: instruction = 16'b0000000000000000;
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                        4'b1101: instruction = 16'b0000000000000000;
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                        4'b1110: instruction = 16'b0000000000000000;
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                        4'b1111: instruction = 16'b0000000000000000;
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                        default: instruction = 16'b0000000000000000;
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         endcase
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endmodule
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`endif

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