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dimamali |
------------------------------------------------------------------------------
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-- LEON3 Demonstration design test bench
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-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library gaisler;
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use gaisler.libdcom.all;
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use gaisler.sim.all;
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use gaisler.jtagtst.all;
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library techmap;
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use techmap.gencomp.all;
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use work.debug.all;
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library gsi;
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use gsi.all;
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use work.config.all; -- configuration
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entity testbench is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW;
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clkperiod : integer := 20; -- system clock period
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romwidth : integer := 32; -- rom data width (8/32)
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romdepth : integer := 16; -- rom address depth
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sramwidth : integer := 32; -- ram data width (8/16/32)
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sramdepth : integer := 18; -- ram address depth
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srambanks : integer := 2 -- number of ram banks
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);
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end;
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architecture behav of testbench is
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constant promfile : string := "prom.srec"; -- rom contents
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constant sramfile : string := "sram.srec"; -- ram contents
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constant sdramfile : string := "sdram.srec"; -- sdram contents
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signal clk : std_logic := '0';
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signal Rst : std_logic := '0'; -- Reset
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constant ct : integer := clkperiod/2;
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signal address : std_logic_vector(27 downto 0) := (others => '0');
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signal data : std_logic_vector(31 downto 0);
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signal ramsn : std_logic;
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signal ramoen : std_logic;
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signal rwen : std_logic;
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signal ramben : std_logic_vector(3 downto 0);
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signal romsn : std_logic;
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signal iosn : std_ulogic;
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signal oen : std_ulogic;
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signal writen : std_ulogic;
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signal brdyn : std_ulogic;
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signal bexcn : std_ulogic;
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signal wdog : std_ulogic;
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signal dsutx, dsurx, dsubre, dsuact : std_ulogic;
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signal dsurst : std_ulogic;
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signal test : std_ulogic;
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signal error : std_logic;
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signal gpio : std_logic_vector(6 downto 0);
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signal GND : std_ulogic := '0';
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signal VCC : std_ulogic := '1';
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signal NC : std_ulogic := 'Z';
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signal clk2 : std_ulogic := '1';
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signal txd1, rxd1 : std_ulogic;
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signal txd2, rxd2 : std_ulogic;
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signal etx_clk, erx_clk, erx_dv, erx_er, erx_col, erx_crs, etx_en, etx_er : std_logic:='0';
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signal erxd, etxd: std_logic_vector(3 downto 0):=(others=>'0');
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signal erxdt, etxdt: std_logic_vector(7 downto 0):=(others=>'0');
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signal emdc, emdio: std_logic; --dummy signal for the mdc,mdio in the phy which is not used
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signal gtx_clk : std_ulogic := '0';
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constant lresp : boolean := false;
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signal flash_byten : std_logic;
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signal flash_rpn : std_logic;
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signal sram_pwrdwn : std_logic;
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signal sram_gwen : std_logic;
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signal sram_adsc : std_logic;
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signal sram_adsp : std_logic;
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signal sram_adv : std_logic;
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signal can_txd : std_logic;
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signal can_rxd : std_logic;
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signal ramclk : std_logic;
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signal datazz : std_logic;
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signal tck, trst, tdi, tms, tdo : std_ulogic;
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begin
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-- clock and reset
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clk <= not clk after ct * 1 ns;
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rst <= dsurst;
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dsubre <= '0';
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rxd1 <= txd1;
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d3 : entity work.leon3mp
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generic map ( fabtech, memtech, padtech, clktech, disas, dbguart, pclow )
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port map (rst, clk, error, address(20 downto 2), data,
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dsutx, dsurx, dsubre, dsuact, txd1, rxd1,
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ramsn, ramoen, ramben, rwen, oen, writen, romsn, iosn, ramclk, gpio,
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flash_byten, flash_rpn, sram_pwrdwn, sram_gwen,
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sram_adsc, sram_adsp, sram_adv, can_txd, can_rxd,
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emdio, etx_clk, erx_clk, erxd, erx_dv, erx_er, erx_col, erx_crs,
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etxd, etx_en, etx_er, emdc, open, tck, tms, tdi, trst, tdo);
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prom0 : for i in 0 to (romwidth/8)-1 generate
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sr0 : sram generic map (index => i, abits => romdepth, fname => promfile)
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port map (address(romdepth+1 downto 2), data(31-i*8 downto 24-i*8), romsn,
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rwen, oen);
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end generate;
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sssram0 : for i in 0 to 1 generate
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u0 : entity gsi.g880e18bt --generic map (fname => sramfile)
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port map(
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A88 => address(18 downto 0),
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DQa(9) => datazz, DQa(8 downto 1) => data(i*16+7 downto i*16),
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DQb(9) => datazz, DQb(8 downto 1) => data(i*16+15 downto i*16+8),
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nBa => ramben(i*2), nBb => ramben(i*2+1),
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CK => ramclk, nBW => rwen, nGW => sram_gwen,
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nE1 => ramsn, E2 => '1', nE3 => ramsn,
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nG => ramoen, nADV => sram_adv, nADSC => sram_adsc,
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nADSP => sram_adsp, Zz => sram_pwrdwn, nFT => '1',
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nLBO => '0');
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end generate;
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phy0 : if (CFG_GRETH = 1) generate
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emdio <= 'H';
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erxd <= erxdt(3 downto 0);
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etxdt <= "0000" & etxd;
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p0: phy
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generic map(base1000_t_fd => 0, base1000_t_hd => 0)
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port map(rst, emdio, etx_clk, erx_clk, erxdt, erx_dv,
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erx_er, erx_col, erx_crs, etxdt, etx_en, etx_er, emdc, gtx_clk);
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end generate;
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error <= 'H'; -- ERROR pull-up
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iuerr : process
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begin
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wait for 2500 ns;
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if to_x01(error) = '1' then wait on error; end if;
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assert (to_x01(error) = '1')
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report "*** IU in error mode, simulation halted ***"
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severity failure ;
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end process;
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data <= buskeep(data), (others => 'H') after 250 ns;
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-- data <= (others => 'Z');
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test0 : grtestmod
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port map ( rst, clk, error, address(21 downto 2), data,
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iosn, oen, writen, brdyn);
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dsucom : process
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procedure dsucfg(signal dsurx : in std_ulogic; signal dsutx : out std_ulogic) is
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variable w32 : std_logic_vector(31 downto 0);
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variable c8 : std_logic_vector(7 downto 0);
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constant txp : time := 160 * 1 ns;
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begin
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dsutx <= '1';
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dsurst <= '0';
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wait for 500 ns;
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dsurst <= '1';
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wait;
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wait for 5000 ns;
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txc(dsutx, 16#55#, txp); -- sync uart
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-- txc(dsutx, 16#c0#, txp);
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-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
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-- txa(dsutx, 16#00#, 16#00#, 16#02#, 16#ae#, txp);
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-- txc(dsutx, 16#c0#, txp);
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-- txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
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-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#ae#, txp);
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-- txc(dsutx, 16#c0#, txp);
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-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#24#, txp);
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-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#03#, txp);
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-- txc(dsutx, 16#c0#, txp);
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-- txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
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-- txa(dsutx, 16#00#, 16#00#, 16#06#, 16#fc#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#2f#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#91#, 16#00#, 16#00#, 16#00#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#6f#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#11#, 16#00#, 16#00#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#00#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#40#, 16#00#, 16#04#, txp);
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txa(dsutx, 16#00#, 16#02#, 16#20#, 16#01#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#02#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#40#, 16#00#, 16#43#, 16#10#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#0f#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#91#, 16#40#, 16#00#, 16#24#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#24#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#91#, 16#70#, 16#00#, 16#00#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#03#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#00#, 16#00#, 16#20#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#ff#, 16#ff#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#40#, 16#00#, 16#48#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#00#, 16#12#, txp);
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txc(dsutx, 16#c0#, txp);
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txa(dsutx, 16#90#, 16#40#, 16#00#, 16#60#, txp);
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txa(dsutx, 16#00#, 16#00#, 16#12#, 16#10#, txp);
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txc(dsutx, 16#80#, txp);
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txa(dsutx, 16#90#, 16#00#, 16#00#, 16#00#, txp);
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rxi(dsurx, w32, txp, lresp);
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txc(dsutx, 16#a0#, txp);
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txa(dsutx, 16#40#, 16#00#, 16#00#, 16#00#, txp);
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rxi(dsurx, w32, txp, lresp);
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end;
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begin
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dsucfg(dsutx, dsurx);
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wait;
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end process;
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jtagproc : process
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begin
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wait;
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trst <= '1';
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jtagcom(tdo, tck, tms, tdi, 40, 20, 16#40000000#, true);
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wait;
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end process;
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end ;
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