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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-clock-gate/] [Makefile] - Blame information for rev 2

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GRLIB=../..
TOP=leon3mp
BOARD=gr-pci-xc2v
#BOARD=gr-cpci-xc2v
include $(GRLIB)/boards/$(BOARD)/Makefile.inc
DEVICE=$(PART)-$(PACKAGE)$(SPEED)
UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
EFFORT=std
XSTOPT=
VHDLSYNFILES=config.vhd ahbrom.vhd clkgate.vhd leon3mp.vhd
VHDLSIMFILES=testbench.vhd
SIMTOP=testbench
SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
CLEAN=soft-clean
 
LIBSKIP = dare
 
include $(GRLIB)/bin/Makefile
include $(GRLIB)/software/leon3/Makefile
 
 
##################  project specific targets ##########################
 

Line No.	Rev	Author	Line
1	2	dimamali	`GRLIB=../..`
2			`TOP=leon3mp`
3			`BOARD=gr-pci-xc2v`
4			`#BOARD=gr-cpci-xc2v`
5			`include $(GRLIB)/boards/$(BOARD)/Makefile.inc`
6			`DEVICE=$(PART)-$(PACKAGE)$(SPEED)`
7			`UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf`
8			`QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf`
9			`EFFORT=std`
10			`XSTOPT=`
11			`VHDLSYNFILES=config.vhd ahbrom.vhd clkgate.vhd leon3mp.vhd`
12			`VHDLSIMFILES=testbench.vhd`
13			`SIMTOP=testbench`
14			`SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc`
15			`BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut`
16			`CLEAN=soft-clean`
17
18			`LIBSKIP = dare`
19
20			`include $(GRLIB)/bin/Makefile`
21			`include $(GRLIB)/software/leon3/Makefile`
22
23
24			`################## project specific targets ##########################`
25

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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-clock-gate/] [Makefile] - Blame information for rev 2