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dimamali |
-----------------------------------------------------------------------------
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-- LEON3 Demonstration design
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-- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib, techmap;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use techmap.gencomp.all;
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library gaisler;
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use gaisler.memctrl.all;
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use gaisler.leon3.all;
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use gaisler.uart.all;
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use gaisler.misc.all;
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use gaisler.jtag.all;
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-- pragma translate_off
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use gaisler.sim.all;
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-- pragma translate_on
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library esa;
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use esa.memoryctrl.all;
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use work.config.all;
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entity leon3mp is
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generic (
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fabtech : integer := CFG_FABTECH;
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memtech : integer := CFG_MEMTECH;
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padtech : integer := CFG_PADTECH;
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clktech : integer := CFG_CLKTECH;
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disas : integer := CFG_DISAS; -- Enable disassembly to console
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dbguart : integer := CFG_DUART; -- Print UART on console
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pclow : integer := CFG_PCLOW
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);
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port (
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reset : in std_ulogic;
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clk : in std_ulogic; -- 50 MHz main clock
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error : out std_ulogic;
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address : out std_logic_vector(19 downto 2);
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data : inout std_logic_vector(31 downto 0);
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ramsn : out std_logic_vector (1 downto 0);
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mben : out std_logic_vector (3 downto 0);
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oen : out std_ulogic;
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writen : out std_ulogic;
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dsubre : in std_ulogic;
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dsuact : out std_ulogic;
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txd1 : out std_ulogic; -- UART1 tx data
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rxd1 : in std_ulogic; -- UART1 rx data
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pio : inout std_logic_vector(17 downto 0); -- I/O port
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-- switch : in std_logic_vector(7 downto 0); -- switches
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-- button : in std_logic_vector(2 downto 0); -- buttons
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ps2clk : inout std_logic;
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ps2data : inout std_logic;
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vid_hsync : out std_ulogic;
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vid_vsync : out std_ulogic;
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vid_r : out std_logic;
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vid_g : out std_logic;
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vid_b : out std_logic
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);
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end;
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architecture rtl of leon3mp is
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constant blength : integer := 12;
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constant fifodepth : integer := 8;
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constant maxahbm : integer := CFG_NCPU+
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CFG_AHB_JTAG+CFG_SVGA_ENABLE;
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signal vcc, gnd : std_logic_vector(4 downto 0);
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signal memi : memory_in_type;
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signal memo : memory_out_type;
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signal wpo : wprot_out_type;
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signal sdi : sdctrl_in_type;
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signal sdo : sdram_out_type;
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signal sdo2, sdo3 : sdctrl_out_type;
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signal apbi : apb_slv_in_type;
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signal apbo : apb_slv_out_vector := (others => apb_none);
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signal ahbsi : ahb_slv_in_type;
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signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
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signal ahbmi : ahb_mst_in_type;
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signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
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signal clkm, rstn, rstraw, nerror : std_ulogic;
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signal cgi : clkgen_in_type;
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signal cgo : clkgen_out_type;
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signal u1i, u2i, dui : uart_in_type;
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signal u1o, u2o, duo : uart_out_type;
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signal irqi : irq_in_vector(0 to CFG_NCPU-1);
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signal irqo : irq_out_vector(0 to CFG_NCPU-1);
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signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
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signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
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signal dsui : dsu_in_type;
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signal dsuo : dsu_out_type;
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signal gpti : gptimer_in_type;
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signal gpioi : gpio_in_type;
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signal gpioo : gpio_out_type;
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signal lclk, rst : std_ulogic;
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signal tck, tckn, tms, tdi, tdo : std_ulogic;
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signal kbdi : ps2_in_type;
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signal kbdo : ps2_out_type;
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signal vgao : apbvga_out_type;
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signal clkval : std_logic_vector(1 downto 0);
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constant BOARD_FREQ : integer := 50000; -- input frequency in KHz
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constant CPU_FREQ : integer := BOARD_FREQ * CFG_CLKMUL / CFG_CLKDIV; -- cpu frequency in KHz
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constant IOAEN : integer := 0;
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signal stati : ahbstat_in_type;
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signal dac_clk, clk1x, vid_clock, video_clk, clkvga : std_logic; -- signals to vga_clkgen.
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signal clk_sel : std_logic_vector(1 downto 0);
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attribute keep : boolean;
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attribute syn_keep : boolean;
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attribute syn_preserve : boolean;
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attribute syn_keep of video_clk : signal is true;
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attribute syn_preserve of video_clk : signal is true;
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attribute keep of video_clk : signal is true;
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begin
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----------------------------------------------------------------------
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--- Reset and Clock generation -------------------------------------
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----------------------------------------------------------------------
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vcc <= (others => '1'); gnd <= (others => '0');
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cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
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clk_pad : clkpad generic map (tech => padtech) port map (clk, lclk);
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clkgen0 : clkgen -- clock generator
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generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
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CFG_CLK_NOFB, 0, 0, 0, BOARD_FREQ)
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port map (lclk, lclk, clkm, open, open, open, open, cgi, cgo, open, clk1x);
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resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
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rst0 : rstgen -- reset generator
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generic map (acthigh => 1)
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port map (rst, clkm, cgo.clklock, rstn, rstraw);
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----------------------------------------------------------------------
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--- AHB CONTROLLER --------------------------------------------------
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----------------------------------------------------------------------
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ahb0 : ahbctrl -- AHB arbiter/multiplexer
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generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
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rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
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ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
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port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
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----------------------------------------------------------------------
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--- LEON3 processor and DSU -----------------------------------------
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----------------------------------------------------------------------
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l3 : if CFG_LEON3 = 1 generate
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cpu : for i in 0 to CFG_NCPU-1 generate
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u0 : leon3s -- LEON3 processor
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generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
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0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
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CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
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CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
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CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
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CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
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port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
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irqi(i), irqo(i), dbgi(i), dbgo(i));
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end generate;
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nerror <= not dbgo(0).error;
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error_pad : outpad generic map (tech => padtech) port map (error, nerror);
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dsugen : if CFG_DSU = 1 generate
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dsu0 : dsu3 -- LEON3 Debug Support Unit
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generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
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ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
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port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
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dsui.enable <= '1';
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dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
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dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
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end generate;
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end generate;
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nodsu : if CFG_DSU = 0 generate
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dsuo.tstop <= '0'; dsuo.active <= '0';
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end generate;
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-- dcomgen : if CFG_AHB_UART = 1 generate
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-- dcom0: ahbuart -- Debug UART
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-- generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
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-- port map (rstn, clkm, dui, duo, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
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-- dsurx_pad : inpad generic map (tech => padtech) port map (rxd2, dui.rxd);
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-- dsutx_pad : outpad generic map (tech => padtech) port map (txd2, duo.txd);
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-- end generate;
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-- nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
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ahbjtaggen0 :if CFG_AHB_JTAG = 1 generate
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ahbjtag0 : ahbjtag generic map(tech => fabtech, hindex => CFG_NCPU)
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port map(rstn, clkm, tck, tms, tdi, tdo, ahbmi, ahbmo(CFG_NCPU),
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open, open, open, open, open, open, open, gnd(0));
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end generate;
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----------------------------------------------------------------------
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--- Memory controllers ----------------------------------------------
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----------------------------------------------------------------------
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memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "00";
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mctrl0 : mctrl generic map (hindex => 0, pindex => 0,
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rommask => 16#000#, iomask => 16#000#,
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paddr => 0, srbanks => 1, ram8 => CFG_MCTRL_RAM8BIT,
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ram16 => CFG_MCTRL_RAM16BIT, sden => CFG_MCTRL_SDEN,
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invclk => CFG_CLK_NOFB, sepbus => CFG_MCTRL_SEPBUS)
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port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
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addr_pad : outpadv generic map (width => 18, tech => padtech)
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port map (address, memo.address(19 downto 2));
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ramsa_pad : outpad generic map (tech => padtech)
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port map (ramsn(0), memo.ramsn(0));
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ramsb_pad : outpad generic map (tech => padtech)
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port map (ramsn(1), memo.ramsn(0));
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oen_pad : outpad generic map (tech => padtech)
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port map (oen, memo.oen);
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wri_pad : outpad generic map (tech => padtech)
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port map (writen, memo.writen);
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mben_pads : outpadv generic map (tech => padtech, width => 4)
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port map (mben, memo.mben);
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data_pads : iopadvv generic map (tech => padtech, width => 32)
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port map (data, memo.data(31 downto 0),
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memo.vbdrive(31 downto 0), memi.data(31 downto 0));
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----------------------------------------------------------------------
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--- APB Bridge and various periherals -------------------------------
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----------------------------------------------------------------------
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bpromgen : if CFG_AHBROMEN /= 0 generate
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brom : entity work.ahbrom
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generic map (hindex => 6, haddr => CFG_AHBRODDR, pipe => CFG_AHBROPIP)
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port map ( rstn, clkm, ahbsi, ahbso(6));
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end generate;
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----------------------------------------------------------------------
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--- APB Bridge and various periherals -------------------------------
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----------------------------------------------------------------------
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apb0 : apbctrl -- AHB/APB bridge
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generic map (hindex => 1, haddr => CFG_APBADDR, nslaves => 16)
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port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
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ua1 : if CFG_UART1_ENABLE /= 0 generate
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uart1 : apbuart -- UART 1
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generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
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fifosize => CFG_UART1_FIFO)
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port map (rstn, clkm, apbi, apbo(1), u1i, u1o);
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u1i.extclk <= '0';
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rxd1_pad : inpad generic map (tech => padtech) port map (rxd1, u1i.rxd);
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txd1_pad : outpad generic map (tech => padtech) port map (txd1, u1o.txd);
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end generate;
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noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
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irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
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irqctrl0 : irqmp -- interrupt controller
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generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
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port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
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end generate;
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irq3 : if CFG_IRQ3_ENABLE = 0 generate
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x : for i in 0 to CFG_NCPU-1 generate
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irqi(i).irl <= "0000";
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end generate;
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apbo(2) <= apb_none;
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end generate;
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gpt : if CFG_GPT_ENABLE /= 0 generate
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timer0 : gptimer -- timer unit
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generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
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sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
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nbits => CFG_GPT_TW)
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port map (rstn, clkm, apbi, apbo(3), gpti, open);
|
307 |
|
|
gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
|
308 |
|
|
end generate;
|
309 |
|
|
|
310 |
|
|
nogpt : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
|
311 |
|
|
|
312 |
|
|
kbd : if CFG_KBD_ENABLE /= 0 generate
|
313 |
|
|
ps20 : apbps2 generic map(pindex => 5, paddr => 5, pirq => 5)
|
314 |
|
|
port map(rstn, clkm, apbi, apbo(5), kbdi, kbdo);
|
315 |
|
|
end generate;
|
316 |
|
|
nokbd : if CFG_KBD_ENABLE = 0 generate
|
317 |
|
|
apbo(5) <= apb_none; kbdo <= ps2o_none;
|
318 |
|
|
end generate;
|
319 |
|
|
kbdclk_pad : iopad generic map (tech => padtech)
|
320 |
|
|
port map (ps2clk,kbdo.ps2_clk_o, kbdo.ps2_clk_oe, kbdi.ps2_clk_i);
|
321 |
|
|
kbdata_pad : iopad generic map (tech => padtech)
|
322 |
|
|
port map (ps2data, kbdo.ps2_data_o, kbdo.ps2_data_oe, kbdi.ps2_data_i);
|
323 |
|
|
|
324 |
|
|
clkdiv : process(clk1x, rstn)
|
325 |
|
|
begin
|
326 |
|
|
if rstn = '0' then clkval <= "00";
|
327 |
|
|
elsif rising_edge(clk1x) then
|
328 |
|
|
clkval <= clkval + 1;
|
329 |
|
|
end if;
|
330 |
|
|
end process;
|
331 |
|
|
|
332 |
|
|
vga : if CFG_VGA_ENABLE /= 0 generate
|
333 |
|
|
vga0 : apbvga generic map(memtech => memtech, pindex => 6, paddr => 6)
|
334 |
|
|
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao);
|
335 |
|
|
video_clock_pad : outpad generic map ( tech => padtech)
|
336 |
|
|
port map (vid_clock, dac_clk);
|
337 |
|
|
dac_clk <= not video_clk;
|
338 |
|
|
b1 : techbuf generic map (2, virtex2) port map (clkval(0), video_clk);
|
339 |
|
|
end generate;
|
340 |
|
|
|
341 |
|
|
svga : if CFG_SVGA_ENABLE /= 0 generate
|
342 |
|
|
clkvga <= clkval(1) when clk_sel = "00" else clkval(0) when clk_sel = "01" else clkm;
|
343 |
|
|
b1 : techbuf generic map (2, virtex2) port map (clkvga, video_clk);
|
344 |
|
|
svga0 : svgactrl generic map(memtech => memtech, pindex => 6, paddr => 6,
|
345 |
|
|
hindex => CFG_NCPU+CFG_AHB_JTAG,
|
346 |
|
|
clk0 => 40000, clk1 => 20000, clk2 => 25000)
|
347 |
|
|
port map(rstn, clkm, video_clk, apbi, apbo(6), vgao, ahbmi,
|
348 |
|
|
ahbmo(CFG_NCPU+CFG_AHB_JTAG), clk_sel);
|
349 |
|
|
dac_clk <= not video_clk;
|
350 |
|
|
video_clock_pad : outpad generic map ( tech => padtech)
|
351 |
|
|
port map (vid_clock, dac_clk);
|
352 |
|
|
end generate;
|
353 |
|
|
|
354 |
|
|
novga : if (CFG_VGA_ENABLE = 0 and CFG_SVGA_ENABLE = 0) generate
|
355 |
|
|
apbo(6) <= apb_none; vgao <= vgao_none;
|
356 |
|
|
end generate;
|
357 |
|
|
|
358 |
|
|
vert_sync_pad : outpad generic map (tech => padtech)
|
359 |
|
|
port map (vid_vsync, vgao.vsync);
|
360 |
|
|
horiz_sync_pad : outpad generic map (tech => padtech)
|
361 |
|
|
port map (vid_hsync, vgao.hsync);
|
362 |
|
|
video_out_r_pad : outpad generic map (tech => padtech)
|
363 |
|
|
port map (vid_r, vgao.video_out_r(7));
|
364 |
|
|
video_out_g_pad : outpad generic map (tech => padtech)
|
365 |
|
|
port map (vid_g, vgao.video_out_g(7));
|
366 |
|
|
video_out_b_pad : outpad generic map (tech => padtech)
|
367 |
|
|
port map (vid_b, vgao.video_out_b(7));
|
368 |
|
|
|
369 |
|
|
gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GPIO unit
|
370 |
|
|
grgpio0: grgpio
|
371 |
|
|
generic map(pindex => 8, paddr => 8, imask => CFG_GRGPIO_IMASK, nbits => 18)
|
372 |
|
|
port map(rst => rstn, clk => clkm, apbi => apbi, apbo => apbo(8),
|
373 |
|
|
gpioi => gpioi, gpioo => gpioo);
|
374 |
|
|
pio_pads : iopadvv generic map (width => 18, tech => padtech)
|
375 |
|
|
port map (pio, gpioo.dout(17 downto 0), gpioo.oen(17 downto 0),
|
376 |
|
|
gpioi.din(17 downto 0));
|
377 |
|
|
|
378 |
|
|
end generate;
|
379 |
|
|
|
380 |
|
|
-----------------------------------------------------------------------
|
381 |
|
|
--- AHB RAM ----------------------------------------------------------
|
382 |
|
|
-----------------------------------------------------------------------
|
383 |
|
|
|
384 |
|
|
ocram : if CFG_AHBRAMEN = 1 generate
|
385 |
|
|
ahbram0 : ahbram generic map (hindex => 7, haddr => CFG_AHBRADDR,
|
386 |
|
|
tech => CFG_MEMTECH, kbytes => CFG_AHBRSZ)
|
387 |
|
|
port map ( rstn, clkm, ahbsi, ahbso(7));
|
388 |
|
|
end generate;
|
389 |
|
|
|
390 |
|
|
-----------------------------------------------------------------------
|
391 |
|
|
--- Drive unused bus elements ---------------------------------------
|
392 |
|
|
-----------------------------------------------------------------------
|
393 |
|
|
|
394 |
|
|
-- nam1 : for i in (CFG_NCPU+FG_AHB_UART+CFG_GRETH+CFG_AHB_JTAG) to NAHBMST-1 generate
|
395 |
|
|
-- ahbmo(i) <= ahbm_none;
|
396 |
|
|
-- end generate;
|
397 |
|
|
-- nap0 : for i in 11 to NAPBSLV-1 generate apbo(i) <= apb_none; end generate;
|
398 |
|
|
-- nah0 : for i in 8 to NAHBSLV-1 generate ahbso(i) <= ahbs_none; end generate;
|
399 |
|
|
|
400 |
|
|
-----------------------------------------------------------------------
|
401 |
|
|
--- Test report module ----------------------------------------------
|
402 |
|
|
-----------------------------------------------------------------------
|
403 |
|
|
|
404 |
|
|
-- pragma translate_off
|
405 |
|
|
|
406 |
|
|
test0 : ahbrep generic map (hindex => 4, haddr => 16#200#)
|
407 |
|
|
port map (rstn, clkm, ahbsi, ahbso(4));
|
408 |
|
|
|
409 |
|
|
-- pragma translate_on
|
410 |
|
|
|
411 |
|
|
-----------------------------------------------------------------------
|
412 |
|
|
--- Boot message ----------------------------------------------------
|
413 |
|
|
-----------------------------------------------------------------------
|
414 |
|
|
|
415 |
|
|
-- pragma translate_off
|
416 |
|
|
x : report_version
|
417 |
|
|
generic map (
|
418 |
|
|
msg1 => "LEON3 Digilent XC3S1000 Demonstration design",
|
419 |
|
|
msg2 => "GRLIB Version " & tost(LIBVHDL_VERSION/1000) & "." & tost((LIBVHDL_VERSION mod 1000)/100)
|
420 |
|
|
& "." & tost(LIBVHDL_VERSION mod 100) & ", build " & tost(LIBVHDL_BUILD),
|
421 |
|
|
msg3 => "Target technology: " & tech_table(fabtech) & ", memory library: " & tech_table(memtech),
|
422 |
|
|
mdel => 1
|
423 |
|
|
);
|
424 |
|
|
-- pragma translate_on
|
425 |
|
|
end;
|