URL
https://opencores.org/ocsvn/mips_enhanced/mips_enhanced/trunk
Details |
Compare with Previous |
View Log
| Line No. |
Rev |
Author |
Line |
| 1 |
2 |
dimamali |
GRLIB=../..
|
| 2 |
|
|
TOP=leon3mp
|
| 3 |
|
|
BOARD=digilent-xup-xc2vp
|
| 4 |
|
|
include $(GRLIB)/boards/$(BOARD)/Makefile.inc
|
| 5 |
|
|
DEVICE=$(PART)-$(PACKAGE)$(SPEED)
|
| 6 |
|
|
#UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
|
| 7 |
|
|
UCF=leon3mp.ucf
|
| 8 |
|
|
QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
|
| 9 |
|
|
EFFORT=high
|
| 10 |
|
|
SYNPOPT="set_option -pipe 1; set_option -retiming 1; set_option -write_apr_constraint 0"
|
| 11 |
|
|
XSTOPT=-uc leon3mp.xcf
|
| 12 |
|
|
VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
|
| 13 |
|
|
VHDLSIMFILES=testbench.vhd
|
| 14 |
|
|
SIMTOP=testbench
|
| 15 |
|
|
#SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc
|
| 16 |
|
|
SDCFILE=default.sdc
|
| 17 |
|
|
BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
|
| 18 |
|
|
CLEAN=soft-clean
|
| 19 |
|
|
|
| 20 |
|
|
TECHLIBS = unisim
|
| 21 |
|
|
LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF usbhc hynix \
|
| 22 |
|
|
tmtc openchip cypress ihp gleichmann opencores spw fmf gsi spansion
|
| 23 |
|
|
DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan pci leon3ft ambatest \
|
| 24 |
|
|
ata can usb spacewire grusbhc
|
| 25 |
|
|
FILESKIP = grcan.vhd i2cmst.vhd
|
| 26 |
|
|
|
| 27 |
|
|
include $(GRLIB)/bin/Makefile
|
| 28 |
|
|
include $(GRLIB)/software/leon3/Makefile
|
| 29 |
|
|
|
| 30 |
|
|
#XLDFLAGS = -N -g -O2 -qprom -qsvt bdinit.c dump.s -L./ lib3tests.a -lmkprom3
|
| 31 |
|
|
|
| 32 |
|
|
################## project specific targets ##########################
|
| 33 |
|
|
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.