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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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--============================================================================--
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-- Design unit : PE architecture (architecture declarations)
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--
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-- File name : pe_arch.vhd
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--
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-- Purpose : Wrapper for simulation
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--
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-- Library : PE_Lib
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--
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-- Authors : Mr Sandi Alexander Habinc
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-- Gaisler Research
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--
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-- Contact : mailto:support@gaisler.com
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-- http://www.gaisler.com
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--
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-- Disclaimer : All information is provided "as is", there is no warranty that
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-- the information is correct or suitable for any purpose,
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-- neither implicit nor explicit.
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--============================================================================--
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--============================== Architecture ================================--
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library IEEE;
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use IEEE.Std_Logic_1164.all;
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library PE_Lib;
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use PE_Lib.PE_Package.all;
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architecture Wrapper of PE is
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component WildFpga is
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port (
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Clocks_F_Clk: in std_logic;
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Clocks_M_Clk: in std_logic;
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Clocks_P_Clk: in std_logic;
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Clocks_K_Clk: in std_logic;
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Clocks_IO_Clk: in std_logic;
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Clocks_M_Clk_Out_PE: out std_logic;
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Clocks_M_Clk_Out_CB_Ctrl: out std_logic;
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Clocks_M_Clk_Out_Right_Mem: out std_logic;
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Clocks_M_Clk_Out_Left_Mem: out std_logic;
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Clocks_P_Clk_Out_PE: out std_logic;
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Clocks_P_Clk_Out_CB_Ctrl: out std_logic;
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Reset_Reset: in std_logic;
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Audio_Audio: out std_logic;
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LAD_Bus_Addr_Data: inout std_logic_vector (31 downto 0);
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LAD_Bus_AS_n: in std_logic;
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LAD_Bus_DS_n: in std_logic;
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LAD_Bus_WR_n: in std_logic;
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LAD_Bus_CS_n: in std_logic;
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LAD_Bus_Reg_n: in std_logic;
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LAD_Bus_Ack_n: out std_logic;
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LAD_Bus_Int_Req_n: out std_logic;
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LAD_Bus_DMA_0_Data_OK_n: out std_logic;
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LAD_Bus_DMA_0_Burst_OK: out std_logic;
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LAD_Bus_DMA_1_Data_OK_n: out std_logic;
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LAD_Bus_DMA_1_Burst_OK: out std_logic;
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LAD_Bus_Reg_Data_OK_n: out std_logic;
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LAD_Bus_Reg_Burst_OK: out std_logic;
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LAD_Bus_Force_K_Clk_n: out std_logic;
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LAD_Bus_Reserved: out std_logic;
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Left_Mem_Addr: out std_logic_vector (18 downto 0);
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Left_Mem_Data: inout std_logic_vector (35 downto 0);
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Left_Mem_Byte_WR_n: out std_logic_vector (3 downto 0);
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Left_Mem_CS_n: out std_logic;
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Left_Mem_CE_n: out std_logic;
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Left_Mem_WE_n: out std_logic;
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Left_Mem_OE_n: out std_logic;
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Left_Mem_Sleep_EN: out std_logic;
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Left_Mem_Load_EN_n: out std_logic;
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Left_Mem_Burst_Mode: out std_logic;
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Right_Mem_Addr: out std_logic_vector (18 downto 0);
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Right_Mem_Data: inout std_logic_vector (35 downto 0);
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Right_Mem_Byte_WR_n: out std_logic_vector (3 downto 0);
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Right_Mem_CS_n: out std_logic;
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Right_Mem_CE_n: out std_logic;
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Right_Mem_WE_n: out std_logic;
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Right_Mem_OE_n: out std_logic;
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Right_Mem_Sleep_EN: out std_logic;
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Right_Mem_Load_EN_n: out std_logic;
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Right_Mem_Burst_Mode: out std_logic;
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Left_IO: inout std_logic_vector (12 downto 0);
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Right_IO: inout std_logic_vector (12 downto 0));
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end component;
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signal Clocks_M_Clk_Out_Right_Del: std_logic;
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signal Clocks_M_Clk_Out_Left_Del: std_logic;
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begin
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Init_PE_Pads ( Pads );
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Pads.Clocks.M_Clk_Out_Right_Mem <= transport Clocks_M_Clk_Out_Right_Del after 2 ns;
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Pads.Clocks.M_Clk_Out_Left_Mem <= transport Clocks_M_Clk_Out_Left_Del after 2 ns;
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FPGA: WildFpga
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port map (
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Clocks_F_Clk => Pads.Clocks.F_Clk,
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Clocks_M_Clk => Pads.Clocks.M_Clk,
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Clocks_P_Clk => Pads.Clocks.P_Clk,
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Clocks_K_Clk => Pads.Clocks.K_Clk,
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Clocks_IO_Clk => Pads.Clocks.IO_Clk,
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Clocks_M_Clk_Out_PE => Pads.Clocks.M_Clk_Out_PE,
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Clocks_M_Clk_Out_CB_Ctrl => Pads.Clocks.M_Clk_Out_CB_Ctrl,
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Clocks_M_Clk_Out_Right_Mem => Clocks_M_Clk_Out_Right_Del,
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Clocks_M_Clk_Out_Left_Mem => Clocks_M_Clk_Out_Left_Del,
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Clocks_P_Clk_Out_PE => Pads.Clocks.P_Clk_Out_PE,
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Clocks_P_Clk_Out_CB_Ctrl => Pads.Clocks.P_Clk_Out_CB_Ctrl,
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Reset_Reset => Pads.Reset,
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Audio_Audio => Pads.Audio,
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LAD_Bus_Addr_Data => Pads.LAD_Bus.Addr_Data,
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LAD_Bus_AS_n => Pads.LAD_Bus.AS_n,
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LAD_Bus_DS_n => Pads.LAD_Bus.DS_n,
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LAD_Bus_WR_n => Pads.LAD_Bus.WR_n,
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LAD_Bus_CS_n => Pads.LAD_Bus.CS_n,
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LAD_Bus_Reg_n => Pads.LAD_Bus.Reg_n,
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LAD_Bus_Ack_n => Pads.LAD_Bus.Ack_n,
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LAD_Bus_Int_Req_n => Pads.LAD_Bus.Int_Req_n,
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LAD_Bus_DMA_0_Data_OK_n => Pads.LAD_Bus.DMA_0_Data_OK_n,
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LAD_Bus_DMA_0_Burst_OK => Pads.LAD_Bus.DMA_0_Burst_OK,
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LAD_Bus_DMA_1_Data_OK_n => Pads.LAD_Bus.DMA_1_Data_OK_n,
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LAD_Bus_DMA_1_Burst_OK => Pads.LAD_Bus.DMA_1_Burst_OK,
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LAD_Bus_Reg_Data_OK_n => Pads.LAD_Bus.Reg_Data_OK_n,
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LAD_Bus_Reg_Burst_OK => Pads.LAD_Bus.Reg_Burst_OK,
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LAD_Bus_Force_K_Clk_n => Pads.LAD_Bus.Force_K_Clk_n,
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LAD_Bus_Reserved => Pads.LAD_Bus.Reserved,
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Left_Mem_Addr => Pads.Left_Mem.Addr,
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Left_Mem_Data => Pads.Left_Mem.Data,
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Left_Mem_Byte_WR_n => Pads.Left_Mem.Byte_WR_n,
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Left_Mem_CS_n => Pads.Left_Mem.CS_n,
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Left_Mem_CE_n => Pads.Left_Mem.CE_n,
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Left_Mem_WE_n => Pads.Left_Mem.WE_n,
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Left_Mem_OE_n => Pads.Left_Mem.OE_n,
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Left_Mem_Sleep_EN => Pads.Left_Mem.Sleep_EN,
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Left_Mem_Load_EN_n => Pads.Left_Mem.Load_EN_n,
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Left_Mem_Burst_Mode => Pads.Left_Mem.Burst_Mode,
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Right_Mem_Addr => Pads.Right_Mem.Addr,
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Right_Mem_Data => Pads.Right_Mem.Data,
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Right_Mem_Byte_WR_n => Pads.Right_Mem.Byte_WR_n,
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Right_Mem_CS_n => Pads.Right_Mem.CS_n,
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Right_Mem_CE_n => Pads.Right_Mem.CE_n,
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Right_Mem_WE_n => Pads.Right_Mem.WE_n,
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Right_Mem_OE_n => Pads.Right_Mem.OE_n,
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Right_Mem_Sleep_EN => Pads.Right_Mem.Sleep_EN,
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Right_Mem_Load_EN_n => Pads.Right_Mem.Load_EN_n,
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Right_Mem_Burst_Mode => Pads.Right_Mem.Burst_Mode,
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Left_IO => Pads.Left_IO,
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Right_IO => Pads.Right_IO);
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end architecture Wrapper; --==================================================--
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