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[/] [mips_enhanced/] [trunk/] [grlib-gpl-1.0.19-b3188/] [designs/] [leon3-xilinx-ml506/] [README.txt] - Blame information for rev 2

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1 2 dimamali
 
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This leon3 design is tailored to the Xilinx Virtex5 ML506 board
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---------------------------------------------------------------------
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Design specifics:
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* System reset is mapped to the CPU RESET button
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* The serial port is connected to the console UART (UART 1) when
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  dip switch 1 on the GPIO DIP switch is off. Otherwise it is
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  connected to the DSU UART. The DSU BREAK input is mapped
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  on the 'south' push-button.
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* The JTAG DSU interface is enabled and works well with
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  GRMON and Xilinx parallel and USB cabels
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* The GRETH core is enabled and runs without problems at 100 Mbit.
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  Using 1 Gbit is also possible with the commercial grlib version.
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  Ethernet debug link is enabled, default IP is 192.168.0.52.
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* DDR2 is now supported and run OK at 200 MHz. The default frequency
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  is 190 MHz but it's possible to go higher. When changing frequency
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  the delay on the data signals might need to be changed too. How to
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  do this is described in the DDR2SPA section of grip.pdf (see
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  description of SDCFG3 register).
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* The SSRAM can be interfaced with the LEON2 Memory controller.
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  Start GRMON with -ramrws 1 when the LEON2 controller is used.
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* The FLASH memory can be programmed using GRMON
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* The LEON3 processor can run up to 80 - 90 MHz on the board
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  in the typical configuartion.
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* The I2C master is connected to the 'Main' I2C bus. An EEPROM (M24C08)
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  can be accessed at I2C address 0x50.
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* TODO: DVI VGA support
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* Sample output from GRMON is:
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 GRMON LEON debug monitor v1.1.25
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 Copyright (C) 2004,2005 Gaisler Research - all rights reserved.
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 For latest updates, go to http://www.gaisler.com/
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 Comments or bug-reports to support@gaisler.com
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 ethernet startup.
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 Device ID: : 0x506
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 GRLIB build version: 2603
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 initialising ................
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 detected frequency:  81 MHz
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 Component                            Vendor
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 LEON3 SPARC V8 Processor             Gaisler Research
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 AHB Debug UART                       Gaisler Research
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 AHB Debug JTAG TAP                   Gaisler Research
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 GR Ethernet MAC                      Gaisler Research
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 DDR2 Controller                      Gaisler Research
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 AHB/APB Bridge                       Gaisler Research
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 LEON3 Debug Support Unit             Gaisler Research
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 LEON2 Memory Controller              European Space Agency
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 Generic APB UART                     Gaisler Research
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 Multi-processor Interrupt Ctrl       Gaisler Research
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 Modular Timer Unit                   Gaisler Research
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 Keyboard PS/2 interface              Gaisler Research
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 Keyboard PS/2 interface              Gaisler Research
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 General purpose I/O port             Gaisler Research
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 AMBA Wrapper for OC I2C-master       Gaisler Research
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 AHB status register                  Gaisler Research
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 Use command 'info sys' to print a detailed report of attached cores
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grlib> info sys
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00.01:003   Gaisler Research  LEON3 SPARC V8 Processor (ver 0x0)
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             ahb master 0
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01.01:007   Gaisler Research  AHB Debug UART (ver 0x0)
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             ahb master 1
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             apb: 80000700 - 80000800
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             baud rate 115200, ahb frequency 81.00
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02.01:01c   Gaisler Research  AHB Debug JTAG TAP (ver 0x0)
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             ahb master 2
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03.01:01d   Gaisler Research  GR Ethernet MAC (ver 0x0)
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             ahb master 3, irq 12
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             apb: 80000b00 - 80000c00
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             edcl ip 192.168.0.52, buffer 2 kbyte
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00.01:02e   Gaisler Research  DDR2 Controller (ver 0x0)
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             ahb: 40000000 - 60000000
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             ahb: fff00100 - fff00200
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             64-bit DDR2 : 1 * 256 Mbyte @ 0x40000000
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                          190 MHz, col 10, ref 7.8 us
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01.01:006   Gaisler Research  AHB/APB Bridge (ver 0x0)
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             ahb: 80000000 - 80100000
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02.01:004   Gaisler Research  LEON3 Debug Support Unit (ver 0x1)
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             ahb: 90000000 - a0000000
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             AHB trace 128 lines, stack pointer 0x4ffffff0
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             CPU#0 win 8, hwbp 2, itrace 128, lddel 1
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                   icache 2 * 8 kbyte, 32 byte/line lru
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                   dcache 1 * 8 kbyte, 16 byte/line lru
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03.04:00f   European Space Agency  LEON2 Memory Controller (ver 0x1)
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             ahb: 00000000 - 20000000
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             ahb: 20000000 - 40000000
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             ahb: c0000000 - c2000000
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             apb: 80000000 - 80000100
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             16-bit prom @ 0x00000000
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01.01:00c   Gaisler Research  Generic APB UART (ver 0x1)
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             irq 2
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             apb: 80000100 - 80000200
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             baud rate 38400
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02.01:00d   Gaisler Research  Multi-processor Interrupt Ctrl (ver 0x3)
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             apb: 80000200 - 80000300
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03.01:011   Gaisler Research  Modular Timer Unit (ver 0x0)
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             irq 8
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             apb: 80000300 - 80000400
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             8-bit scaler, 2 * 32-bit timers, divisor 81
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04.01:060   Gaisler Research  Keyboard PS/2 interface (ver 0x1)
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             irq 4
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             apb: 80000400 - 80000500
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05.01:060   Gaisler Research  Keyboard PS/2 interface (ver 0x1)
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             irq 5
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             apb: 80000500 - 80000600
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08.01:01a   Gaisler Research  General purpose I/O port (ver 0x0)
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             apb: 80000800 - 80000900
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0c.01:028   Gaisler Research  AMBA Wrapper for OC I2C-master (ver 0x0)
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             irq 11
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             apb: 80000c00 - 80000d00
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0f.01:052   Gaisler Research  AHB status register (ver 0x0)
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             irq 7
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             apb: 80000f00 - 80001000
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grlib> fla
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 Intel-style 16-bit flash on D[31:16]
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 Manuf.    Intel
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 Device    Strataflash P30
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 Device ID 5444ffff008e4399
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 User   ID ffffffffffffffff
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 1 x 32 Mbyte = 32 Mbyte total @ 0x00000000
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 CFI info
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 flash family  : 1
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 flash size    : 256 Mbit
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 erase regions : 2
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 erase blocks  : 259
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 write buffer  : 64 bytes
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 lock-down     : yes
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 region  0     : 255 blocks of 128 Kbytes
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 region  1     : 4 blocks of 32 Kbytes
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grlib> i2c read 0x50 0x00 10
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 00:    ff      ff      ff      ff
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 04:    ff      ff      ff      ff
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 08:    ff      ff
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grlib>

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