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Prompt for target technology

CONFIG_SYN_INFERRED

  Selects the target technology for memory and pads.

  The following are available:

  - Inferred: Generic FPGA or ASIC targets if your synthesis tool

    is capable of inferring RAMs and pads automatically.

  - Actel ProAsic/P/3 and Axellerator FPGAs

  - Altera: Any Altera FPGA family

  - ATC18: Atmel-Nantes 0.18 um rad-hard CMOS

  - IHP25: IHP 0.25 um CMOS

  - Lattice : EC/ECP/XP FPGAs

  - UMC-0.18 : UMC 0.18 um CMOS with Virtual Silicon libraries

  - Xilinx-Spartan/2/3: Xilinx Spartan/2/3 libraries

  - Xilinx-Spartan3E: Xilinx Spartan3E libraries

  - Xilinx-Virtex/E: Xilinx Virtex/E libraries

  - Xilinx-Virtex2/4/5: Xilinx Virtex2/4/5 libraries

Ram library

CONFIG_MEM_VIRAGE

  Select RAM generators for ASIC targets.

Infer ram

CONFIG_SYN_INFER_RAM

  Say Y here if you want the synthesis tool to infer your

  RAM automatically. Say N to directly instantiate technology-

  specific RAM cells for the selected target technology package.

Infer pads

CONFIG_SYN_INFER_PADS

  Say Y here if you want the synthesis tool to infer pads.

  Say N to directly instantiate technology-specific pads from

  the selected target technology package.

No async reset

CONFIG_SYN_NO_ASYNC

  Say Y here if you disable asynchronous reset in some of the IP cores.

  Might be necessary if the target library does not have cells with

  asynchronous set/reset.

Use Virtex CLKDLL for clock synchronisation

CONFIG_CLK_INFERRED

  Certain target technologies include clock generators to scale or

  phase-adjust the system and SDRAM clocks. This is currently supported

  for Xilinx and Altera FPGAs. Depending on technology, you can select

  to use the Xilinx CKLDLL macro (Virtex, VirtexE, Spartan1/2), the

  Xilinx DCM (Virtex-2, Spartan3, Virtex-4), or the Altera ALTDLL

  (Stratix, Cyclone). Choose the 'inferred' option if you are not

  using Xilinx or Altera FPGAs.

  Using a technology specific clock generator is necessary to

  re-syncronize the SDRAM clock. For this to work, connect the

  external SDCLK signal with PLLREF.

Clock multiplier

CONFIG_CLK_MUL

  When using the Xilinx DCM or Altera ALTPLL, the system clock can

  be multiplied with a factor of 2 - 32, and divided by a factor of

  1 - 32. This makes it possible to generate almost any desired

  processor frequency. When using the Xilinx CLKDLL generator,

  the resulting frequency scale factor (mul/div) must be one of

  1/2, 1 or 2.

  WARNING: The resulting clock must be within the limits specified

  by the target FPGA family.

Clock divider

CONFIG_CLK_DIV

  When using the Xilinx DCM or Altera ALTPLL, the system clock can

  be multiplied with a factor of 2 - 32, and divided by a factor of

  1 - 32. This makes it possible to generate almost any desired

  processor frequency. When using the Xilinx CLKDLL generator,

  the resulting frequency scale factor (mul/div) must be one of

  1/2, 1 or 2.

  WARNING: The resulting clock must be within the limits specified

  by the target FPGA family.

System clock multiplier

CONFIG_CLKDLL_1_2

  The Xilinx CLKDLL can scale the input clock with a factor of 0.5, 1.0,

  or 2.0. Useful when the target board has an oscillator with a too high

  (or low) frequency for your design. The divided clock will be used as the

  main clock for the whole processor (except PCI and ethernet clocks).

System clock multiplier

CONFIG_DCM_2_3

  The Xilinx DCM and Altera ALTDLL can scale the input clock with a large

  range of factors. Useful when the target board has an oscillator with a

  too high (or low) frequency for your design. The divided clock will

  be used as the main clock for the whole processor (except PCI and

  ethernet clocks). NOTE: the resulting frequency must be at least

  24 MHz or the DCM and ALTDLL might not work.

Enable CLKDLL for PCI clock

CONFIG_PCI_CLKDLL

  Say Y here to re-synchronize the PCI clock using a

  Virtex BUFGDLL macro. Will improve PCI clock-to-output

  delays on the expense of input-setup requirements.

Use PCI clock system clock

CONFIG_PCI_SYSCLK

  Say Y here to the PCI clock to generate the system clock.

  The PCI clock can be scaled using the DCM or CLKDLL to

  generate a suitable processor clock.

External SDRAM clock feedback

CONFIG_CLK_NOFB

  Say Y here to disable the external clock feedback to synchronize the

  SDRAM clock. This option is necessary if your board or design does not

  have an external clock feedback that is connected to the pllref input

  of the clock generator.

CONFIG_AHB_DEFMST

  Sets the default AHB master (see AMBA 2.0 specification for definition).

  Should not be set to a value larger than the number of AHB masters - 1.

  For highest processor performance, leave it at 0.

Default AHB master

CONFIG_AHB_RROBIN

  Say Y here to enable round-robin arbitration of the AHB bus. A N will

  select fixed priority, with the master with the highest bus index having

  the highest priority.

Support AHB split-transactions

CONFIG_AHB_SPLIT

  Say Y here to enable AHB split-transaction support in the AHB arbiter.

  Unless you actually have an AHB slave that can generate AHB split

  responses, say N and save some gates.

Default AHB master

CONFIG_AHB_IOADDR

  Selects the MSB adddress (HADDR[31:20]) of the AHB IO area, as defined

  in the plug&play extentions of the AMBA bus. Should be kept to FFF

  unless you really know what you are doing.

APB bridge address

CONFIG_APB_HADDR

  Selects the MSB adddress (HADDR[31:20]) of the APB bridge. Should be

  kept at 800 for software compatibility.

DSU enable

CONFIG_DSU_UART

  Say Y to enable the AHB uart (serial-to-AHB). This is the most

  commonly used debug communication link.

JTAG Enable

CONFIG_DSU_JTAG

  Say Y to enable the JTAG debug link (JTAG-to-AHB). Debugging is done

  with GRMON through the boards JTAG chain at speed of 300 kbits/s.

  Supported JTAG cables are Xilinx Parallel Cable III and IV.

On-chip ram

CONFIG_AHBRAM_ENABLE

  Say Y here to add a block on on-chip ram to the AHB bus. The ram

  provides 0-waitstates read access and 0/1 waitstates write access.

  All AHB burst types are supported, as well as 8-, 16- and 32-bit

  data size.

On-chip ram size

CONFIG_AHBRAM_SZ1

  Set the size of the on-chip AHB ram. The ram is infered/instantiated

  as four byte-wide ram slices to allow byte and half-word write

  accesses. It is therefore essential that the target package can

  infer byte-wide rams. This is currently supported on the generic,

  virtex, virtex2, proasic and axellerator targets.

On-chip ram address

CONFIG_AHBRAM_START

  Set the start address of AHB RAM (HADDR[31:20]). The RAM will occupy

  a 1 Mbyte slot at the selected address. Default is A00, corresponding

  to AHB address 0xA0000000.

Gaisler Ethernet MAC enable

CONFIG_GRETH_ENABLE

  Say Y here to enable the Gaisler Research Ethernet MAC . The MAC has

  one AHB master interface to read and write packets to memory, and one

  APB slave interface for accessing the control registers.

Gaisler Ethernet 1G MAC enable

CONFIG_GRETH_GIGA

  Say Y here to enable the Gaisler Research 1000 Mbit Ethernet MAC .

  The 1G MAC is only available in the commercial version of GRLIB,

  so do NOT enable it if you are using the GPL version.

CONFIG_GRETH_FIFO4

  Set the depth of the receive and transmit FIFOs in the MAC core.

  The MAC core will perform AHB burst read/writes with half the

  size of the FIFO depth.

PCI interface type

CONFIG_PCI_SIMPLE_TARGET

  The target-only PCI interface provides a simple target interface

  without fifos. It is small and robust, and is suitable to be used

  for DSU communications via PCI.

PCI interface type

CONFIG_PCI_MASTER_TARGET

  The master-target PCI interface provides a high-performance 32-bit

  PCI interface with configurable FIFOs and optional DMA channel.

PCI interface type

CONFIG_PCI_MASTER_TARGET_DMA

  Say Y here to enable a DMA controller in the PCI master-target core.

  The DMA controller can perform PCI<->memory data transfers

  independently of the processor.

PCI vendor id

CONFIG_PCI_VENDORID

  Sets the PCI vendor ID in the PCI configuration area.

PCI device id

CONFIG_PCI_DEVICEID

  Sets the PCI device ID in the PCI configuration area.

PCI initiator address

CONFIG_PCI_HADDR

  Sets the MSB AHB adress (HADDR[31:20]) of the PCI initiator area.

PCI FIFO depth

CONFIG_PCI_FIFO8

  The number words in the PCI FIFO buffers in the master-target

  core. The master interface uses four 33-bit wide FIFOs, while the

  target interface uses two.

PCI trace buffer

CONFIG_PCI_TRACE

  The PCI trace buffer implements a simple on-chip logic analyzer

  to trace the PCI signals. The PCI AD bus and most control signals

  are stored in a circular buffer, and can be read out by the DSU

  or any other AHB master. See the manual for detailed operation.

  Only available for target technologies with dual-port rams.

PCI trace buffer depth

CONFIG_PCI_TRACE256

  Select the number of entries in the PCI trace buffer. Each entry

  will use 6 bytes of on-chip (block) ram.