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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: ahbtrace
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-- File: ahbtrace.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: AHB trace unit
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library grlib;
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use grlib.amba.all;
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use grlib.stdlib.all;
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use grlib.devices.all;
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library techmap;
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use techmap.gencomp.all;
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library gaisler;
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entity ahbtrace is
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generic (
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hindex : integer := 0;
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ioaddr : integer := 16#000#;
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iomask : integer := 16#E00#;
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tech : integer := DEFMEMTECH;
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irq : integer := 0;
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kbytes : integer := 1);
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port (
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rst : in std_ulogic;
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clk : in std_ulogic;
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ahbmi : in ahb_mst_in_type;
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ahbsi : in ahb_slv_in_type;
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ahbso : out ahb_slv_out_type
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);
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end;
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architecture rtl of ahbtrace is
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constant TBUFABITS : integer := log2(kbytes) + 6;
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constant TIMEBITS : integer := 32;
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constant hconfig : ahb_config_type := (
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4 => ahb_iobar (ioaddr, iomask),
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others => zero32);
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type tracebuf_in_type is record
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addr : std_logic_vector(11 downto 0);
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data : std_logic_vector(127 downto 0);
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enable : std_logic;
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write : std_logic_vector(3 downto 0);
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end record;
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type tracebuf_out_type is record
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data : std_logic_vector(127 downto 0);
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end record;
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type trace_break_reg is record
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addr : std_logic_vector(31 downto 2);
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mask : std_logic_vector(31 downto 2);
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read : std_logic;
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write : std_logic;
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end record;
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type regtype is record
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haddr : std_logic_vector(31 downto 0);
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hwrite : std_logic;
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htrans : std_logic_vector(1 downto 0);
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hsize : std_logic_vector(2 downto 0);
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hburst : std_logic_vector(2 downto 0);
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hwdata : std_logic_vector(31 downto 0);
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hmaster : std_logic_vector(3 downto 0);
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hmastlock : std_logic;
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hsel : std_logic;
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hready : std_logic;
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hready2 : std_logic;
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hready3 : std_logic;
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ahbactive : std_logic;
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timer : std_logic_vector(TIMEBITS-1 downto 0);
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aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
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enable : std_logic; -- trace enable
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bahb : std_logic; -- break on AHB watchpoint hit
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bhit : std_logic; -- breakpoint hit
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dcnten : std_logic; -- delay counter enable
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delaycnt : std_logic_vector(TBUFABITS - 1 downto 0); -- delay counter
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tbreg1 : trace_break_reg;
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tbreg2 : trace_break_reg;
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end record;
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signal tbi : tracebuf_in_type;
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signal tbo : tracebuf_out_type;
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signal enable : std_logic_vector(1 downto 0);
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signal r, rin : regtype;
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begin
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ctrl : process(rst, ahbmi, ahbsi, r, tbo)
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variable v : regtype;
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variable vabufi : tracebuf_in_type;
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variable regsd : std_logic_vector(31 downto 0); -- data from registers
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variable aindex : std_logic_vector(TBUFABITS - 1 downto 0); -- buffer index
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variable bphit : std_logic;
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variable bufdata : std_logic_vector(127 downto 0);
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variable hirq : std_logic_vector(NAHBIRQ-1 downto 0);
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begin
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v := r; regsd := (others => '0'); vabufi.enable := '0';
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vabufi.data := (others => '0'); vabufi.addr := (others => '0');
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vabufi.write := (others => '0'); bphit := '0';
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v.hready := r.hready2; v.hready2 := r.hready3; v.hready3 := '0';
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bufdata := tbo.data;
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hirq := (others => '0'); hirq(irq) := r.bhit;
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-- trace buffer index and delay counters
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if r.enable = '1' then v.timer := r.timer + 1; end if;
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aindex := r.aindex + 1;
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-- check for AHB watchpoints
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if (ahbsi.hready and r.ahbactive ) = '1' then
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if ((((r.tbreg1.addr xor r.haddr(31 downto 2)) and r.tbreg1.mask) = zero32(29 downto 0)) and
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(((r.tbreg1.read and not r.hwrite) or (r.tbreg1.write and r.hwrite)) = '1'))
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or ((((r.tbreg2.addr xor r.haddr(31 downto 2)) and r.tbreg2.mask) = zero32(29 downto 0)) and
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(((r.tbreg2.read and not r.hwrite) or (r.tbreg2.write and r.hwrite)) = '1'))
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then
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if (r.enable = '1') and (r.dcnten = '0') and
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(r.delaycnt /= zero32(TBUFABITS-1 downto 0))
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then v.dcnten := '1';
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else bphit := '1'; v.enable := '0'; end if;
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end if;
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end if;
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-- generate buffer inputs
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vabufi.write := "0000";
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if r.enable = '1' then
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vabufi.addr(TBUFABITS-1 downto 0) := r.aindex;
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vabufi.data(127 downto 96) := r.timer;
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vabufi.data(95) := bphit;
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vabufi.data(94 downto 80) := ahbmi.hirq(15 downto 1);
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vabufi.data(79) := r.hwrite;
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vabufi.data(78 downto 77) := r.htrans;
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vabufi.data(76 downto 74) := r.hsize;
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vabufi.data(73 downto 71) := r.hburst;
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vabufi.data(70 downto 67) := r.hmaster;
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vabufi.data(66) := r.hmastlock;
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vabufi.data(65 downto 64) := ahbmi.hresp;
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if r.hwrite = '1' then
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vabufi.data(63 downto 32) := ahbsi.hwdata;
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else
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vabufi.data(63 downto 32) := ahbmi.hrdata;
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end if;
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vabufi.data(31 downto 0) := r.haddr;
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else
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vabufi.addr(TBUFABITS-1 downto 0) := r.haddr(TBUFABITS+3 downto 4);
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vabufi.data := ahbsi.hwdata & ahbsi.hwdata &
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ahbsi.hwdata & ahbsi.hwdata;
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end if;
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-- write trace buffer
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if r.enable = '1' then
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if (r.ahbactive and ahbsi.hready) = '1' then
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v.aindex := aindex;
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vabufi.enable := '1'; vabufi.write := "1111";
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end if;
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end if;
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-- trace buffer delay counter handling
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if (r.dcnten = '1') then
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if (r.delaycnt = zero32(TBUFABITS-1 downto 0)) then
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v.enable := '0'; v.dcnten := '0';
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end if;
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v.delaycnt := r.delaycnt - 1;
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end if;
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-- save AHB transfer parameters
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if (ahbsi.hready = '1' ) then
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v.haddr := ahbsi.haddr; v.hwrite := ahbsi.hwrite; v.htrans := ahbsi.htrans;
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v.hsize := ahbsi.hsize; v.hburst := ahbsi.hburst;
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v.hmaster := ahbsi.hmaster; v.hmastlock := ahbsi.hmastlock;
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end if;
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if r.hsel = '1' then v.hwdata := ahbsi.hwdata; end if;
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if ahbsi.hready = '1' then
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v.hsel := ahbsi.hsel(hindex);
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v.ahbactive := ahbsi.htrans(1);
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end if;
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-- AHB slave access to DSU registers and trace buffers
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if (r.hsel and not r.hready) = '1' then
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if r.haddr(16) = '0' then -- registers
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v.hready := '1';
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case r.haddr(4 downto 2) is
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when "000" =>
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regsd((TBUFABITS + 15) downto 16) := r.delaycnt;
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regsd(1 downto 0) := r.dcnten & r.enable;
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if r.hwrite = '1' then
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v.delaycnt := ahbsi.hwdata((TBUFABITS+ 15) downto 16);
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v.dcnten := ahbsi.hwdata(1);
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v.enable := ahbsi.hwdata(0);
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end if;
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when "001" =>
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regsd((TBUFABITS - 1 + 4) downto 4) := r.aindex;
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if r.hwrite = '1' then
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v.aindex := ahbsi.hwdata((TBUFABITS- 1) downto 0);
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end if;
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when "010" =>
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regsd((TIMEBITS - 1) downto 0) := r.timer;
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if r.hwrite = '1' then
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v.timer := ahbsi.hwdata((TIMEBITS- 1) downto 0);
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end if;
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when "100" =>
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regsd(31 downto 2) := r.tbreg1.addr;
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if r.hwrite = '1' then
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v.tbreg1.addr := ahbsi.hwdata(31 downto 2);
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end if;
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when "101" =>
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regsd := r.tbreg1.mask & r.tbreg1.read & r.tbreg1.write;
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if r.hwrite = '1' then
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v.tbreg1.mask := ahbsi.hwdata(31 downto 2);
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v.tbreg1.read := ahbsi.hwdata(1);
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v.tbreg1.write := ahbsi.hwdata(0);
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end if;
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when "110" =>
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regsd(31 downto 2) := r.tbreg2.addr;
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if r.hwrite = '1' then
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v.tbreg2.addr := ahbsi.hwdata(31 downto 2);
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end if;
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when others =>
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regsd := r.tbreg2.mask & r.tbreg2.read & r.tbreg2.write;
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if r.hwrite = '1' then
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v.tbreg2.mask := ahbsi.hwdata(31 downto 2);
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v.tbreg2.read := ahbsi.hwdata(1);
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v.tbreg2.write := ahbsi.hwdata(0);
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end if;
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end case;
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v.hwdata := regsd;
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259 |
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else -- read/write access to trace buffer
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260 |
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if r.hwrite = '1' then v.hready := '1'; else v.hready2 := not (r.hready2 or r.hready); end if;
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261 |
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vabufi.enable := not r.enable;
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262 |
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bufdata := tbo.data;
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263 |
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case r.haddr(3 downto 2) is
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264 |
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when "00" =>
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v.hwdata := bufdata(127 downto 96);
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266 |
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if r.hwrite = '1' then
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vabufi.write(3) := vabufi.enable;
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268 |
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end if;
|
269 |
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when "01" =>
|
270 |
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v.hwdata := bufdata(95 downto 64);
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271 |
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if r.hwrite = '1' then
|
272 |
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vabufi.write(2) := vabufi.enable;
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273 |
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end if;
|
274 |
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when "10" =>
|
275 |
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v.hwdata := bufdata(63 downto 32);
|
276 |
|
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if r.hwrite = '1' then
|
277 |
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vabufi.write(1) := vabufi.enable;
|
278 |
|
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end if;
|
279 |
|
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when others =>
|
280 |
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v.hwdata := bufdata(31 downto 0);
|
281 |
|
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if r.hwrite = '1' then
|
282 |
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vabufi.write(0) := vabufi.enable;
|
283 |
|
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end if;
|
284 |
|
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end case;
|
285 |
|
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end if;
|
286 |
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end if;
|
287 |
|
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|
288 |
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if ((ahbsi.hsel(hindex) and ahbsi.hready) = '1') and
|
289 |
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((ahbsi.htrans = HTRANS_BUSY) or (ahbsi.htrans = HTRANS_IDLE))
|
290 |
|
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then v.hready := '1'; end if;
|
291 |
|
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|
292 |
|
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if rst = '0' then
|
293 |
|
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v.ahbactive := '0'; v.enable := '0'; v.timer := (others => '0');
|
294 |
|
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v.hsel := '0'; v.dcnten := '0'; v.bhit := '0';
|
295 |
|
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v.tbreg1.read := '0'; v.tbreg1.write := '0';
|
296 |
|
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v.tbreg2.read := '0'; v.tbreg2.write := '0';
|
297 |
|
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end if;
|
298 |
|
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|
299 |
|
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tbi <= vabufi;
|
300 |
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rin <= v;
|
301 |
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|
302 |
|
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ahbso.hconfig <= hconfig;
|
303 |
|
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ahbso.hirq <= hirq;
|
304 |
|
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ahbso.hsplit <= (others => '0');
|
305 |
|
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ahbso.hcache <= '0';
|
306 |
|
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ahbso.hrdata <= r.hwdata;
|
307 |
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ahbso.hready <= r.hready;
|
308 |
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ahbso.hindex <= hindex;
|
309 |
|
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|
310 |
|
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end process;
|
311 |
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|
312 |
|
|
ahbso.hresp <= HRESP_OKAY;
|
313 |
|
|
|
314 |
|
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regs : process(clk)
|
315 |
|
|
begin if rising_edge(clk) then r <= rin; end if; end process;
|
316 |
|
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|
317 |
|
|
-- mem0 : tbufmem
|
318 |
|
|
-- generic map (tech => tech, tbuf => kbytes) port map (clk, tbi, tbo);
|
319 |
|
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|
320 |
|
|
enable <= tbi.enable & tbi.enable;
|
321 |
|
|
mem0 : for i in 0 to 1 generate
|
322 |
|
|
ram0 : syncram64 generic map (tech => tech, abits => TBUFABITS)
|
323 |
|
|
port map (clk, tbi.addr(TBUFABITS-1 downto 0), tbi.data(((i*64)+63) downto (i*64)),
|
324 |
|
|
tbo.data(((i*64)+63) downto (i*64)), enable, tbi.write(i*2+1 downto i*2));
|
325 |
|
|
end generate;
|
326 |
|
|
|
327 |
|
|
-- pragma translate_off
|
328 |
|
|
bootmsg : report_version
|
329 |
|
|
generic map ("ahbtrace" & tost(hindex) &
|
330 |
|
|
": AHB Trace Buffer, " & tost(kbytes) & " kbytes");
|
331 |
|
|
-- pragma translate_on
|
332 |
|
|
|
333 |
|
|
end;
|
334 |
|
|
|
335 |
|
|
|