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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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--============================================================================--
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-- Design unit : DMA2AHB_TestPackage (package declaration)
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--
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-- File name : dma2ahb_tp.vhd
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--
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-- Purpose : Interface package for AMBA AHB master interface with DMA input
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--
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-- Reference : AMBA(TM) Specification (Rev 2.0), ARM IHI 0011A,
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-- 13th May 1999, issue A, first release, ARM Limited
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-- The document can be retrieved from http://www.arm.com
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-- AMBA is a trademark of ARM Limited.
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-- ARM is a registered trademark of ARM Limited.
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--
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-- Note : Naming convention according to AMBA(TM) Specification:
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-- Signal names are in upper case, except for the following:
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-- A lower case 'n' in the name indicates that the signal
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-- is active low.
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-- Constant names are in upper case.
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-- The least significant bit of an array is located to the right,
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-- carrying the index number zero.
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--
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-- Limitations : See DMA2AHB VHDL core
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--
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-- Library : {independent}
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--
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-- Authors : Mr Sandi Habinc
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-- Gaisler Research AB
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-- Forsta Langgantan 19
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-- SE-413 27 Göteborg
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-- Sweden
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--
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-- Contact : mailto:sandi@gaisler.com
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-- http://www.gaisler.com
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--
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-- Disclaimer : All information is provided "as is", there is no warranty that
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-- the information is correct or suitable for any purpose,
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-- neither implicit nor explicit.
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--
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--------------------------------------------------------------------------------
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-- Version Author Date Changes
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--
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-- 1.4 SH 1 Jul 2005 New package
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-- 1.5 SH 1 Sep 2005 New library TOPNET
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-- 1.6 SH 20 Sep 2005 Added transparent HSIZE support
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-- 1.8 SH 10 Nov 2005 Updated DMA2AHB interface usage
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-- 1.9 SH 4 Jan 2006 Burst routines added
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-- Fault reporting priority and timing improved
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-- 1.9.1 SH 12 Jan 2006 Correct DmaComp8
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-- 1.9.2 SH ## ### #### Corrected compare to allow pull-up
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-- Adjusted printouts
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-- 1.9.3 JA 14 Dec 2007 Support for halfword and byte bursts
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-- 1.9.4 MI 4 Aug 2008 Support for Lock
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--------------------------------------------------------------------------------
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library IEEE;
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use IEEE.Std_Logic_1164.all;
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use IEEE.Numeric_Std.all;
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library Std;
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use Std.Standard.all;
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use Std.TextIO.all;
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library GRLIB;
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use GRLIB.AMBA.all;
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use GRLIB.STDIO.all;
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use GRLIB.DMA2AHB_Package.all;
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use GRLIB.STDLIB.all;
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package DMA2AHB_TestPackage is
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-----------------------------------------------------------------------------
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-- Vector of words
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-----------------------------------------------------------------------------
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type Data_Vector is array (Natural range <> ) of
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Std_Logic_Vector(32-1 downto 0);
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-----------------------------------------------------------------------------
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-- Constants for comparison
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-----------------------------------------------------------------------------
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constant DontCare32: Std_Logic_Vector(31 downto 0) := (others => '-');
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constant DontCare24: Std_Logic_Vector(23 downto 0) := (others => '-');
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constant DontCare16: Std_Logic_Vector(15 downto 0) := (others => '-');
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constant DontCare8: Std_Logic_Vector( 7 downto 0) := (others => '-');
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----------------------------------------------------------------------------
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-- Constant for calculating burst lengths
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----------------------------------------------------------------------------
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constant WordSize: integer := 32;
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-----------------------------------------------------------------------------
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-- Initialize AHB interface
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-----------------------------------------------------------------------------
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procedure DMAInit(
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signal HCLK: in Std_ULogic;
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signal dmai: out dma_in_type;
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constant InstancePath: in String := "DMAInit";
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constant ScreenOutput: in Boolean := False);
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-----------------------------------------------------------------------------
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-- AMBA AHB write access
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-----------------------------------------------------------------------------
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procedure DMAWrite(
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constant Address: in Std_Logic_Vector(31 downto 0);
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constant Data: in Std_Logic_Vector(31 downto 0);
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signal HCLK: in Std_ULogic;
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signal dmai: out dma_in_type;
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signal dmao: in dma_out_type;
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variable TP: inout Boolean;
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constant InstancePath: in String := "DMAWrite";
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constant ScreenOutput: in Boolean := False;
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constant cBack2Back: in Boolean := False;
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constant Size: in Integer := 32;
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constant Lock: in Boolean := False);
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-----------------------------------------------------------------------------
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-- AMBA AHB read access
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-----------------------------------------------------------------------------
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procedure DMAQuiet(
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constant Address: in Std_Logic_Vector(31 downto 0);
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variable Data: out Std_Logic_Vector(31 downto 0);
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signal HCLK: in Std_ULogic;
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signal dmai: out dma_in_type;
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signal dmao: in dma_out_type;
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variable TP: inout Boolean;
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constant InstancePath: in String := "DMAQuiet";
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constant ScreenOutput: in Boolean := False;
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constant cBack2Back: in Boolean := False;
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constant Size: in Integer := 32;
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constant Lock: in Boolean := False);
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-----------------------------------------------------------------------------
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-- AMBA AHB read access
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-----------------------------------------------------------------------------
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procedure DMARead(
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constant Address: in Std_Logic_Vector(31 downto 0);
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variable Data: out Std_Logic_Vector(31 downto 0);
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signal HCLK: in Std_ULogic;
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signal dmai: out dma_in_type;
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signal dmao: in dma_out_type;
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variable TP: inout Boolean;
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constant InstancePath: in String := "DMARead";
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constant ScreenOutput: in Boolean := True;
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constant cBack2Back: in Boolean := False;
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constant Size: in Integer := 32;
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constant Lock: in Boolean := False);
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-----------------------------------------------------------------------------
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-- AMBA AHB read access
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-----------------------------------------------------------------------------
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procedure DMAComp(
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constant Address: in Std_Logic_Vector(31 downto 0);
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constant CxData: in Std_Logic_Vector(31 downto 0);
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variable RxData: out Std_Logic_Vector(31 downto 0);
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signal HCLK: in Std_ULogic;
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signal dmai: out dma_in_type;
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signal dmao: in dma_out_type;
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variable TP: inout Boolean;
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constant InstancePath: in String := "DMAComp";
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constant ScreenOutput: in Boolean := False;
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constant cBack2Back: in Boolean := False;
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constant Size: in Integer := 32;
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constant Lock: in Boolean := False);
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-----------------------------------------------------------------------------
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-- AMBA AHB write access
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-----------------------------------------------------------------------------
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procedure DMAWrite16(
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constant Address: in Std_Logic_Vector(31 downto 0);
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constant Data: in Std_Logic_Vector(15 downto 0);
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signal HCLK: in Std_ULogic;
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signal dmai: out dma_in_type;
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signal dmao: in dma_out_type;
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variable TP: inout Boolean;
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constant InstancePath: in String := "DMAWrite16";
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constant ScreenOutput: in Boolean := False;
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constant cBack2Back: in Boolean := False;
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constant Lock: in Boolean := False);
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-----------------------------------------------------------------------------
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-- AMBA AHB read access
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-----------------------------------------------------------------------------
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procedure DMAQuiet16(
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constant Address: in Std_Logic_Vector(31 downto 0);
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variable Data: out Std_Logic_Vector(15 downto 0);
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signal HCLK: in Std_ULogic;
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signal dmai: out dma_in_type;
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signal dmao: in dma_out_type;
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variable TP: inout Boolean;
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constant InstancePath: in String := "DMAQuiet16";
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constant ScreenOutput: in Boolean := False;
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constant cBack2Back: in Boolean := False;
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constant Lock: in Boolean := False);
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-----------------------------------------------------------------------------
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-- AMBA AHB read access
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-----------------------------------------------------------------------------
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procedure DMARead16(
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constant Address: in Std_Logic_Vector(31 downto 0);
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variable Data: out Std_Logic_Vector(15 downto 0);
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signal HCLK: in Std_ULogic;
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signal dmai: out dma_in_type;
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signal dmao: in dma_out_type;
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variable TP: inout Boolean;
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constant InstancePath: in String := "DMARead16";
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constant ScreenOutput: in Boolean := True;
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constant cBack2Back: in Boolean := False;
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constant Lock: in Boolean := False);
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-----------------------------------------------------------------------------
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-- AMBA AHB read access
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-----------------------------------------------------------------------------
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procedure DMAComp16(
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constant Address: in Std_Logic_Vector(31 downto 0);
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constant CxData: in Std_Logic_Vector(15 downto 0);
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variable RxData: out Std_Logic_Vector(15 downto 0);
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signal HCLK: in Std_ULogic;
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signal dmai: out dma_in_type;
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signal dmao: in dma_out_type;
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variable TP: inout Boolean;
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constant InstancePath: in String := "DMAComp16";
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constant ScreenOutput: in Boolean := False;
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constant cBack2Back: in Boolean := False;
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constant Lock: in Boolean := False);
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-----------------------------------------------------------------------------
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-- AMBA AHB write access
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-----------------------------------------------------------------------------
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procedure DMAWrite8(
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constant Address: in Std_Logic_Vector(31 downto 0);
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constant Data: in Std_Logic_Vector( 7 downto 0);
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signal HCLK: in Std_ULogic;
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signal dmai: out dma_in_type;
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signal dmao: in dma_out_type;
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variable TP: inout Boolean;
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constant InstancePath: in String := "DMAWrite8";
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constant ScreenOutput: in Boolean := False;
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constant cBack2Back: in Boolean := False;
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constant Lock: in Boolean := False);
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-----------------------------------------------------------------------------
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-- AMBA AHB read access
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-----------------------------------------------------------------------------
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procedure DMAQuiet8(
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constant Address: in Std_Logic_Vector(31 downto 0);
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variable Data: out Std_Logic_Vector( 7 downto 0);
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signal HCLK: in Std_ULogic;
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signal dmai: out dma_in_type;
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signal dmao: in dma_out_type;
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variable TP: inout Boolean;
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constant InstancePath: in String := "DMAQuiet8";
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constant ScreenOutput: in Boolean := False;
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constant cBack2Back: in Boolean := False;
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constant Lock: in Boolean := False);
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-----------------------------------------------------------------------------
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-- AMBA AHB read access
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-----------------------------------------------------------------------------
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procedure DMARead8(
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constant Address: in Std_Logic_Vector(31 downto 0);
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variable Data: out Std_Logic_Vector( 7 downto 0);
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signal HCLK: in Std_ULogic;
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signal dmai: out dma_in_type;
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signal dmao: in dma_out_type;
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variable TP: inout Boolean;
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constant InstancePath: in String := "DMARead8";
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constant ScreenOutput: in Boolean := True;
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constant cBack2Back: in Boolean := False;
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constant Lock: in Boolean := False);
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-----------------------------------------------------------------------------
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-- AMBA AHB read access
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-----------------------------------------------------------------------------
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procedure DMAComp8(
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constant Address: in Std_Logic_Vector(31 downto 0);
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constant CxData: in Std_Logic_Vector( 7 downto 0);
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variable RxData: out Std_Logic_Vector( 7 downto 0);
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signal HCLK: in Std_ULogic;
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signal dmai: out dma_in_type;
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signal dmao: in dma_out_type;
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variable TP: inout Boolean;
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constant InstancePath: in String := "DMAComp8";
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constant ScreenOutput: in Boolean := False;
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constant cBack2Back: in Boolean := False;
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constant Lock: in Boolean := False);
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-----------------------------------------------------------------------------
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-- AMBA AHB write access
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-----------------------------------------------------------------------------
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procedure DMAWriteQuietBurst(
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constant Address: in Std_Logic_Vector(31 downto 0);
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constant Data: in Data_Vector;
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signal HCLK: in Std_ULogic;
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signal dmai: out dma_in_type;
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signal dmao: in dma_out_type;
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variable TP: inout Boolean;
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constant InstancePath: in String := "DMAWrite";
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constant ScreenOutput: in Boolean := False;
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constant cBack2Back: in Boolean := False;
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constant Size: in Integer := 32;
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constant Beat: in Integer := 1;
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constant Lock: in Boolean := False);
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-----------------------------------------------------------------------------
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-- AMBA AHB write access
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-----------------------------------------------------------------------------
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procedure DMAWriteBurst(
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constant Address: in Std_Logic_Vector(31 downto 0);
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constant Data: in Data_Vector;
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signal HCLK: in Std_ULogic;
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signal dmai: out dma_in_type;
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signal dmao: in dma_out_type;
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variable TP: inout Boolean;
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constant InstancePath: in String := "DMAWrite";
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constant ScreenOutput: in Boolean := False;
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constant cBack2Back: in Boolean := False;
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constant Size: in Integer := 32;
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constant Beat: in Integer := 1;
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constant Lock: in Boolean := False);
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-----------------------------------------------------------------------------
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-- AMBA AHB read access
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-----------------------------------------------------------------------------
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procedure DMAQuietBurst(
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constant Address: in Std_Logic_Vector(31 downto 0);
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variable Data: out Data_Vector;
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signal HCLK: in Std_ULogic;
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signal dmai: out dma_in_type;
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344 |
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signal dmao: in dma_out_type;
|
345 |
|
|
variable TP: inout Boolean;
|
346 |
|
|
constant InstancePath: in String := "DMAQuiet";
|
347 |
|
|
constant ScreenOutput: in Boolean := False;
|
348 |
|
|
constant cBack2Back: in Boolean := False;
|
349 |
|
|
constant Size: in Integer := 32;
|
350 |
|
|
constant Beat: in Integer := 1;
|
351 |
|
|
constant Lock: in Boolean := False);
|
352 |
|
|
|
353 |
|
|
|
354 |
|
|
-----------------------------------------------------------------------------
|
355 |
|
|
-- AMBA AHB read access
|
356 |
|
|
-----------------------------------------------------------------------------
|
357 |
|
|
procedure DMAReadBurst(
|
358 |
|
|
constant Address: in Std_Logic_Vector(31 downto 0);
|
359 |
|
|
variable Data: out Data_Vector;
|
360 |
|
|
signal HCLK: in Std_ULogic;
|
361 |
|
|
signal dmai: out dma_in_type;
|
362 |
|
|
signal dmao: in dma_out_type;
|
363 |
|
|
variable TP: inout Boolean;
|
364 |
|
|
constant InstancePath: in String := "DMARead";
|
365 |
|
|
constant ScreenOutput: in Boolean := True;
|
366 |
|
|
constant cBack2Back: in Boolean := False;
|
367 |
|
|
constant Size: in Integer := 32;
|
368 |
|
|
constant Beat: in Integer := 1;
|
369 |
|
|
constant Lock: in Boolean := False);
|
370 |
|
|
|
371 |
|
|
|
372 |
|
|
-----------------------------------------------------------------------------
|
373 |
|
|
-- AMBA AHB read access
|
374 |
|
|
-----------------------------------------------------------------------------
|
375 |
|
|
procedure DMACompBurst(
|
376 |
|
|
constant Address: in Std_Logic_Vector(31 downto 0);
|
377 |
|
|
variable CxData: in Data_Vector;
|
378 |
|
|
variable RxData: out Data_Vector;
|
379 |
|
|
signal HCLK: in Std_ULogic;
|
380 |
|
|
signal dmai: out dma_in_type;
|
381 |
|
|
signal dmao: in dma_out_type;
|
382 |
|
|
variable TP: inout Boolean;
|
383 |
|
|
constant InstancePath: in String := "DMAComp";
|
384 |
|
|
constant ScreenOutput: in Boolean := False;
|
385 |
|
|
constant cBack2Back: in Boolean := False;
|
386 |
|
|
constant Size: in Integer := 32;
|
387 |
|
|
constant Beat: in Integer := 1;
|
388 |
|
|
constant Lock: in Boolean := False);
|
389 |
|
|
|
390 |
|
|
end package DMA2AHB_TestPackage;
|
391 |
|
|
|
392 |
|
|
package body DMA2AHB_TestPackage is
|
393 |
|
|
-----------------------------------------------------------------------------
|
394 |
|
|
-- Compare function handling '-'
|
395 |
|
|
-----------------------------------------------------------------------------
|
396 |
|
|
function Compare(O, C: in Std_Logic_Vector) return Boolean is
|
397 |
|
|
variable T: Std_Logic_Vector(O'Range) := C;
|
398 |
|
|
variable Result: Boolean;
|
399 |
|
|
begin
|
400 |
|
|
Result := True;
|
401 |
|
|
for i in O'Range loop
|
402 |
|
|
if not (To_X01(O(i))=T(i) or T(i)='-' or T(i)='U') then
|
403 |
|
|
Result := False;
|
404 |
|
|
end if;
|
405 |
|
|
end loop;
|
406 |
|
|
return Result;
|
407 |
|
|
end function Compare;
|
408 |
|
|
|
409 |
|
|
-----------------------------------------------------------------------------
|
410 |
|
|
-- Function declarations
|
411 |
|
|
-----------------------------------------------------------------------------
|
412 |
|
|
function Conv_Std_Logic_Vector(
|
413 |
|
|
constant i: Integer;
|
414 |
|
|
w: Integer)
|
415 |
|
|
return Std_Logic_Vector is
|
416 |
|
|
variable tmp: Std_Logic_Vector(w-1 downto 0);
|
417 |
|
|
begin
|
418 |
|
|
tmp := Std_Logic_Vector(To_UnSigned(i, w));
|
419 |
|
|
return(tmp);
|
420 |
|
|
end;
|
421 |
|
|
|
422 |
|
|
-----------------------------------------------------------------------------
|
423 |
|
|
-- Function declarations
|
424 |
|
|
-----------------------------------------------------------------------------
|
425 |
|
|
function Conv_Integer(
|
426 |
|
|
constant i: Std_Logic_Vector)
|
427 |
|
|
return Integer is
|
428 |
|
|
variable tmp: Integer;
|
429 |
|
|
begin
|
430 |
|
|
tmp := To_Integer(UnSigned(i));
|
431 |
|
|
return(tmp);
|
432 |
|
|
end;
|
433 |
|
|
|
434 |
|
|
-----------------------------------------------------------------------------
|
435 |
|
|
-- Synchronisation with respect to clock and with output offset
|
436 |
|
|
-----------------------------------------------------------------------------
|
437 |
|
|
procedure Synchronise(
|
438 |
|
|
signal Clock: in Std_ULogic;
|
439 |
|
|
constant Offset: in Time := 5 ns;
|
440 |
|
|
constant Enable: in Boolean := True) is
|
441 |
|
|
begin
|
442 |
|
|
if Enable then
|
443 |
|
|
wait until Clock = '1'; -- synchronise
|
444 |
|
|
if Offset > 0 ns then
|
445 |
|
|
wait for Offset; -- output offset delay
|
446 |
|
|
end if;
|
447 |
|
|
end if;
|
448 |
|
|
end procedure Synchronise;
|
449 |
|
|
|
450 |
|
|
-----------------------------------------------------------------------------
|
451 |
|
|
-- Initialize AHB interface
|
452 |
|
|
-----------------------------------------------------------------------------
|
453 |
|
|
procedure DMAInit(
|
454 |
|
|
signal HCLK: in Std_ULogic;
|
455 |
|
|
signal dmai: out dma_in_type;
|
456 |
|
|
constant InstancePath: in String := "DMAInit";
|
457 |
|
|
constant ScreenOutput: in Boolean := False) is
|
458 |
|
|
variable L: Line;
|
459 |
|
|
begin
|
460 |
|
|
Synchronise(HCLK);
|
461 |
|
|
dmai.Reset <= '0';
|
462 |
|
|
dmai.Address <= (others => '0');
|
463 |
|
|
dmai.Request <= '0';
|
464 |
|
|
dmai.Burst <= '0';
|
465 |
|
|
dmai.Beat <= (others => '0');
|
466 |
|
|
dmai.Store <= '0';
|
467 |
|
|
dmai.Data <= (others => '0');
|
468 |
|
|
dmai.Size <= "10";
|
469 |
|
|
dmai.Lock <= '0';
|
470 |
|
|
|
471 |
|
|
if ScreenOutput then
|
472 |
|
|
Write (L, Now, Right, 15);
|
473 |
|
|
Write (L, " : " & InstancePath);
|
474 |
|
|
Write (L, String'(" : AHB initalised"));
|
475 |
|
|
WriteLine(Output, L);
|
476 |
|
|
end if;
|
477 |
|
|
end procedure DMAInit;
|
478 |
|
|
|
479 |
|
|
-----------------------------------------------------------------------------
|
480 |
|
|
-- AMBA AHB write access
|
481 |
|
|
-----------------------------------------------------------------------------
|
482 |
|
|
procedure DMAWriteQuiet(
|
483 |
|
|
constant Address: in Std_Logic_Vector(31 downto 0);
|
484 |
|
|
constant Data: in Std_Logic_Vector(31 downto 0);
|
485 |
|
|
signal HCLK: in Std_ULogic;
|
486 |
|
|
signal dmai: out dma_in_type;
|
487 |
|
|
signal dmao: in dma_out_type;
|
488 |
|
|
variable TP: inout Boolean;
|
489 |
|
|
constant InstancePath: in String := "DMAWrite";
|
490 |
|
|
constant ScreenOutput: in Boolean := False;
|
491 |
|
|
constant cBack2Back: in Boolean := False;
|
492 |
|
|
constant Size: in Integer := 32;
|
493 |
|
|
constant Lock: in Boolean := False) is
|
494 |
|
|
variable L: Line;
|
495 |
|
|
begin
|
496 |
|
|
-- do not synchronise when a back-to-back access is requested
|
497 |
|
|
if not cBack2Back then
|
498 |
|
|
Synchronise(HCLK);
|
499 |
|
|
end if;
|
500 |
|
|
dmai.Reset <= '0';
|
501 |
|
|
dmai.Address <= Address;
|
502 |
|
|
dmai.Request <= '1';
|
503 |
|
|
dmai.Burst <= '0';
|
504 |
|
|
dmai.Beat <= (others => '0');
|
505 |
|
|
dmai.Store <= '1';
|
506 |
|
|
dmai.Data <= Data;
|
507 |
|
|
if Size=32 then
|
508 |
|
|
dmai.Size <= HSIZE32;
|
509 |
|
|
elsif Size=16 then
|
510 |
|
|
dmai.Size <= HSIZE16;
|
511 |
|
|
elsif Size=8 then
|
512 |
|
|
dmai.Size <= HSIZE8;
|
513 |
|
|
else
|
514 |
|
|
report "Unsupported data width"
|
515 |
|
|
severity Failure;
|
516 |
|
|
end if;
|
517 |
|
|
|
518 |
|
|
if Lock then
|
519 |
|
|
dmai.Lock <= '1';
|
520 |
|
|
else
|
521 |
|
|
dmai.Lock <= '0';
|
522 |
|
|
end if;
|
523 |
|
|
|
524 |
|
|
wait for 1 ns;
|
525 |
|
|
if dmao.Grant='0' then
|
526 |
|
|
while dmao.Grant='0' loop
|
527 |
|
|
Synchronise(HCLK, 0 ns);
|
528 |
|
|
end loop;
|
529 |
|
|
else
|
530 |
|
|
Synchronise(HCLK);
|
531 |
|
|
end if;
|
532 |
|
|
|
533 |
|
|
dmai.Reset <= '0';
|
534 |
|
|
dmai.Request <= '0';
|
535 |
|
|
dmai.Store <= '0';
|
536 |
|
|
dmai.Burst <= '0';
|
537 |
|
|
|
538 |
|
|
dmai.Data <= Data;
|
539 |
|
|
|
540 |
|
|
loop
|
541 |
|
|
Synchronise(HCLK);
|
542 |
|
|
while dmao.Ready='0' and dmao.Retry='0' and dmao.Fault='0' loop
|
543 |
|
|
Synchronise(HCLK);
|
544 |
|
|
end loop;
|
545 |
|
|
|
546 |
|
|
if dmao.Fault='1' then
|
547 |
|
|
if ScreenOutput then
|
548 |
|
|
Write (L, Now, Right, 15);
|
549 |
|
|
Write (L, " : " & InstancePath);
|
550 |
|
|
Write (L, String'(" : AHB write access, address: "));
|
551 |
|
|
HWrite(L, Address);
|
552 |
|
|
Write (L, String'(" ERROR reponse "));
|
553 |
|
|
WriteLine(Output, L);
|
554 |
|
|
end if;
|
555 |
|
|
TP := False;
|
556 |
|
|
dmai.Reset <= '0';
|
557 |
|
|
dmai.Address <= (others => '0');
|
558 |
|
|
dmai.Data <= (others => '0');
|
559 |
|
|
dmai.Request <= '0';
|
560 |
|
|
dmai.Store <= '0';
|
561 |
|
|
dmai.Burst <= '0';
|
562 |
|
|
dmai.Beat <= (others => '0');
|
563 |
|
|
dmai.Size <= (others => '0');
|
564 |
|
|
dmai.Lock <= '0';
|
565 |
|
|
Synchronise(HCLK);
|
566 |
|
|
Synchronise(HCLK);
|
567 |
|
|
exit;
|
568 |
|
|
elsif dmao.Ready='1' then
|
569 |
|
|
dmai.Reset <= '0';
|
570 |
|
|
dmai.Address <= (others => '0');
|
571 |
|
|
dmai.Data <= (others => '0');
|
572 |
|
|
dmai.Request <= '0';
|
573 |
|
|
dmai.Store <= '0';
|
574 |
|
|
dmai.Burst <= '0';
|
575 |
|
|
dmai.Beat <= (others => '0');
|
576 |
|
|
dmai.Size <= (others => '0');
|
577 |
|
|
dmai.Lock <= '0';
|
578 |
|
|
exit;
|
579 |
|
|
end if;
|
580 |
|
|
|
581 |
|
|
if dmao.Retry='1' then
|
582 |
|
|
if ScreenOutput then
|
583 |
|
|
Write (L, Now, Right, 15);
|
584 |
|
|
Write (L, " : " & InstancePath);
|
585 |
|
|
Write (L, String'(" : AHB write access, address: "));
|
586 |
|
|
HWrite(L, Address);
|
587 |
|
|
Write (L, String'(" RETRY/SPLIT reponse "));
|
588 |
|
|
WriteLine(Output, L);
|
589 |
|
|
end if;
|
590 |
|
|
end if;
|
591 |
|
|
end loop;
|
592 |
|
|
end procedure DMAWriteQuiet;
|
593 |
|
|
|
594 |
|
|
-----------------------------------------------------------------------------
|
595 |
|
|
-- AMBA AHB write access
|
596 |
|
|
-----------------------------------------------------------------------------
|
597 |
|
|
procedure DMAWrite(
|
598 |
|
|
constant Address: in Std_Logic_Vector(31 downto 0);
|
599 |
|
|
constant Data: in Std_Logic_Vector(31 downto 0);
|
600 |
|
|
signal HCLK: in Std_ULogic;
|
601 |
|
|
signal dmai: out dma_in_type;
|
602 |
|
|
signal dmao: in dma_out_type;
|
603 |
|
|
variable TP: inout Boolean;
|
604 |
|
|
constant InstancePath: in String := "DMAWrite";
|
605 |
|
|
constant ScreenOutput: in Boolean := False;
|
606 |
|
|
constant cBack2Back: in Boolean := False;
|
607 |
|
|
constant Size: in Integer := 32;
|
608 |
|
|
constant Lock: in Boolean := False) is
|
609 |
|
|
variable OK: Boolean := True;
|
610 |
|
|
variable L: Line;
|
611 |
|
|
begin
|
612 |
|
|
DMAWriteQuiet(Address, Data, HCLK, dmai, dmao, OK,
|
613 |
|
|
InstancePath, True, cBack2Back, Size, Lock);
|
614 |
|
|
if ScreenOutput and OK then
|
615 |
|
|
Write (L, Now, Right, 15);
|
616 |
|
|
Write (L, " : " & InstancePath);
|
617 |
|
|
Write (L, String'(" : AHB write access, address: "));
|
618 |
|
|
HWrite(L, Address);
|
619 |
|
|
Write (L, String'(" : data: "));
|
620 |
|
|
HWrite(L, Data);
|
621 |
|
|
WriteLine(Output, L);
|
622 |
|
|
elsif not OK then
|
623 |
|
|
Write (L, Now, Right, 15);
|
624 |
|
|
Write (L, " : " & InstancePath);
|
625 |
|
|
Write (L, String'(" : AHB write access, address: "));
|
626 |
|
|
HWrite(L, Address);
|
627 |
|
|
Write (L, String'(" : ## Failed ##"));
|
628 |
|
|
WriteLine(Output, L);
|
629 |
|
|
TP := False;
|
630 |
|
|
end if;
|
631 |
|
|
end procedure DMAWrite;
|
632 |
|
|
|
633 |
|
|
|
634 |
|
|
-----------------------------------------------------------------------------
|
635 |
|
|
-- AMBA AHB read access
|
636 |
|
|
-----------------------------------------------------------------------------
|
637 |
|
|
procedure DMAQuiet(
|
638 |
|
|
constant Address: in Std_Logic_Vector(31 downto 0);
|
639 |
|
|
variable Data: out Std_Logic_Vector(31 downto 0);
|
640 |
|
|
signal HCLK: in Std_ULogic;
|
641 |
|
|
signal dmai: out dma_in_type;
|
642 |
|
|
signal dmao: in dma_out_type;
|
643 |
|
|
variable TP: inout Boolean;
|
644 |
|
|
constant InstancePath: in String := "DMAQuiet";
|
645 |
|
|
constant ScreenOutput: in Boolean := False;
|
646 |
|
|
constant cBack2Back: in Boolean := False;
|
647 |
|
|
constant Size: in Integer := 32;
|
648 |
|
|
constant Lock: in Boolean := False) is
|
649 |
|
|
variable L: Line;
|
650 |
|
|
begin
|
651 |
|
|
-- do not Synchronise when a back-to-back access is requested
|
652 |
|
|
if not cBack2Back then
|
653 |
|
|
Synchronise(HCLK);
|
654 |
|
|
end if;
|
655 |
|
|
dmai.Reset <= '0';
|
656 |
|
|
dmai.Address <= Address;
|
657 |
|
|
dmai.Request <= '1';
|
658 |
|
|
dmai.Burst <= '0';
|
659 |
|
|
dmai.Beat <= (others => '0');
|
660 |
|
|
dmai.Store <= '0';
|
661 |
|
|
dmai.Data <= (others => '0');
|
662 |
|
|
if Size=32 then
|
663 |
|
|
dmai.Size <= HSIZE32;
|
664 |
|
|
elsif Size=16 then
|
665 |
|
|
dmai.Size <= HSIZE16;
|
666 |
|
|
elsif Size=8 then
|
667 |
|
|
dmai.Size <= HSIZE8;
|
668 |
|
|
else
|
669 |
|
|
report "Unsupported data width"
|
670 |
|
|
severity Failure;
|
671 |
|
|
end if;
|
672 |
|
|
|
673 |
|
|
if Lock then
|
674 |
|
|
dmai.Lock <= '1';
|
675 |
|
|
else
|
676 |
|
|
dmai.Lock <= '0';
|
677 |
|
|
end if;
|
678 |
|
|
|
679 |
|
|
|
680 |
|
|
wait for 1 ns;
|
681 |
|
|
if dmao.Grant='0' then
|
682 |
|
|
while dmao.Grant='0' loop
|
683 |
|
|
Synchronise(HCLK, 0 ns);
|
684 |
|
|
end loop;
|
685 |
|
|
else
|
686 |
|
|
Synchronise(HCLK);
|
687 |
|
|
end if;
|
688 |
|
|
|
689 |
|
|
dmai.Reset <= '0';
|
690 |
|
|
dmai.Data <= (others => '0');
|
691 |
|
|
dmai.Request <= '0';
|
692 |
|
|
dmai.Store <= '0';
|
693 |
|
|
dmai.Burst <= '0';
|
694 |
|
|
dmai.Beat <= (others => '0');
|
695 |
|
|
|
696 |
|
|
loop
|
697 |
|
|
Synchronise(HCLK);
|
698 |
|
|
while dmao.Ready='0' and dmao.Retry='0' and dmao.Fault='0' loop
|
699 |
|
|
Synchronise(HCLK);
|
700 |
|
|
end loop;
|
701 |
|
|
|
702 |
|
|
if dmao.Fault='1' then
|
703 |
|
|
if ScreenOutput then
|
704 |
|
|
Write (L, Now, Right, 15);
|
705 |
|
|
Write (L, " : " & InstancePath);
|
706 |
|
|
Write (L, String'(" : AHB read access, address: "));
|
707 |
|
|
HWrite(L, Address);
|
708 |
|
|
Write (L, String'(" ERROR reponse "));
|
709 |
|
|
WriteLine(Output, L);
|
710 |
|
|
end if;
|
711 |
|
|
TP := False;
|
712 |
|
|
dmai.Reset <= '0';
|
713 |
|
|
dmai.Address <= (others => '0');
|
714 |
|
|
dmai.Data <= (others => '0');
|
715 |
|
|
dmai.Request <= '0';
|
716 |
|
|
dmai.Store <= '0';
|
717 |
|
|
dmai.Burst <= '0';
|
718 |
|
|
dmai.Beat <= (others => '0');
|
719 |
|
|
dmai.Size <= (others => '0');
|
720 |
|
|
Data := (others => 'X');
|
721 |
|
|
Synchronise(HCLK);
|
722 |
|
|
Synchronise(HCLK);
|
723 |
|
|
exit;
|
724 |
|
|
elsif dmao.Ready='1' then
|
725 |
|
|
Data := dmao.Data;
|
726 |
|
|
dmai.Address <= (others => '0');
|
727 |
|
|
dmai.Beat <= (others => '0');
|
728 |
|
|
dmai.Size <= (others => '0');
|
729 |
|
|
exit;
|
730 |
|
|
end if;
|
731 |
|
|
|
732 |
|
|
if dmao.Retry='1' then
|
733 |
|
|
if ScreenOutput then
|
734 |
|
|
Write (L, Now, Right, 15);
|
735 |
|
|
Write (L, " : " & InstancePath);
|
736 |
|
|
Write (L, String'(" : AHB read access, address: "));
|
737 |
|
|
HWrite(L, Address);
|
738 |
|
|
Write (L, String'(" RETRY/SPLIT reponse "));
|
739 |
|
|
WriteLine(Output, L);
|
740 |
|
|
end if;
|
741 |
|
|
end if;
|
742 |
|
|
end loop;
|
743 |
|
|
end procedure DMAQuiet;
|
744 |
|
|
|
745 |
|
|
-----------------------------------------------------------------------------
|
746 |
|
|
-- AMBA AHB read access
|
747 |
|
|
-----------------------------------------------------------------------------
|
748 |
|
|
procedure DMARead(
|
749 |
|
|
constant Address: in Std_Logic_Vector(31 downto 0);
|
750 |
|
|
variable Data: out Std_Logic_Vector(31 downto 0);
|
751 |
|
|
signal HCLK: in Std_ULogic;
|
752 |
|
|
signal dmai: out dma_in_type;
|
753 |
|
|
signal dmao: in dma_out_type;
|
754 |
|
|
variable TP: inout Boolean;
|
755 |
|
|
constant InstancePath: in String := "DMARead";
|
756 |
|
|
constant ScreenOutput: in Boolean := True;
|
757 |
|
|
constant cBack2Back: in Boolean := False;
|
758 |
|
|
constant Size: in Integer := 32;
|
759 |
|
|
constant Lock: in Boolean := False) is
|
760 |
|
|
variable OK: Boolean := True;
|
761 |
|
|
variable L: Line;
|
762 |
|
|
variable Temp: Std_Logic_Vector(31 downto 0);
|
763 |
|
|
begin
|
764 |
|
|
DMAQuiet(Address, Temp, HCLK, dmai, dmao, OK,
|
765 |
|
|
InstancePath, True, cBack2Back, Size, Lock);
|
766 |
|
|
if ScreenOutput and OK then
|
767 |
|
|
Data := Temp;
|
768 |
|
|
Write (L, Now, Right, 15);
|
769 |
|
|
Write (L, " : " & InstancePath);
|
770 |
|
|
Write (L, String'(" : AHB read access, address: "));
|
771 |
|
|
HWrite(L, Address);
|
772 |
|
|
Write (L, String'(" : data: "));
|
773 |
|
|
HWrite(L, Temp);
|
774 |
|
|
WriteLine(Output, L);
|
775 |
|
|
elsif OK then
|
776 |
|
|
Data := Temp;
|
777 |
|
|
else
|
778 |
|
|
Write (L, Now, Right, 15);
|
779 |
|
|
Write (L, " : " & InstancePath);
|
780 |
|
|
Write (L, String'(" : AHB read access, address: "));
|
781 |
|
|
HWrite(L, Address);
|
782 |
|
|
Write (L, String'(" : ## Failed ##"));
|
783 |
|
|
WriteLine(Output, L);
|
784 |
|
|
Data := (others => '-');
|
785 |
|
|
TP := False;
|
786 |
|
|
end if;
|
787 |
|
|
end procedure DMARead;
|
788 |
|
|
|
789 |
|
|
-----------------------------------------------------------------------------
|
790 |
|
|
-- AMBA AHB read access
|
791 |
|
|
-----------------------------------------------------------------------------
|
792 |
|
|
procedure DMAComp(
|
793 |
|
|
constant Address: in Std_Logic_Vector(31 downto 0);
|
794 |
|
|
constant CxData: in Std_Logic_Vector(31 downto 0);
|
795 |
|
|
variable RxData: out Std_Logic_Vector(31 downto 0);
|
796 |
|
|
signal HCLK: in Std_ULogic;
|
797 |
|
|
signal dmai: out dma_in_type;
|
798 |
|
|
signal dmao: in dma_out_type;
|
799 |
|
|
variable TP: inout Boolean;
|
800 |
|
|
constant InstancePath: in String := "DMAComp";
|
801 |
|
|
constant ScreenOutput: in Boolean := False;
|
802 |
|
|
constant cBack2Back: in Boolean := False;
|
803 |
|
|
constant Size: in Integer := 32;
|
804 |
|
|
constant Lock: in Boolean := False) is
|
805 |
|
|
variable OK: Boolean := True;
|
806 |
|
|
variable L: Line;
|
807 |
|
|
variable Data: Std_Logic_Vector(31 downto 0);
|
808 |
|
|
begin
|
809 |
|
|
DMAQuiet(Address, Data, HCLK, dmai, dmao, OK,
|
810 |
|
|
InstancePath, True, cBack2Back, Size, Lock);
|
811 |
|
|
if not OK then
|
812 |
|
|
Write (L, Now, Right, 15);
|
813 |
|
|
Write (L, " : " & InstancePath);
|
814 |
|
|
Write (L, String'(" : AHB read access, address: "));
|
815 |
|
|
HWrite(L, Address);
|
816 |
|
|
Write (L, String'(" : ## Failed ##"));
|
817 |
|
|
WriteLine(Output, L);
|
818 |
|
|
TP := False;
|
819 |
|
|
RxData := (others => '-');
|
820 |
|
|
elsif not Compare(Data, CxData) then
|
821 |
|
|
Write (L, Now, Right, 15);
|
822 |
|
|
Write (L, " : " & InstancePath);
|
823 |
|
|
Write (L, String'(" : AHB read access, address: "));
|
824 |
|
|
HWrite(L, Address);
|
825 |
|
|
Write (L, String'(" : data: "));
|
826 |
|
|
HWrite(L, Data);
|
827 |
|
|
Write (L, String'(" : expected: "));
|
828 |
|
|
HWrite(L, CxData);
|
829 |
|
|
Write (L, String'(" # Error #"));
|
830 |
|
|
WriteLine(Output, L);
|
831 |
|
|
TP := False;
|
832 |
|
|
RxData := Data;
|
833 |
|
|
elsif ScreenOutput then
|
834 |
|
|
Write(L, Now, Right, 15);
|
835 |
|
|
Write(L, " : " & InstancePath);
|
836 |
|
|
Write(L, String'(" : AHB read access, address: "));
|
837 |
|
|
HWrite(L, Address);
|
838 |
|
|
Write(L, String'(" : data: "));
|
839 |
|
|
HWrite(L, Data);
|
840 |
|
|
WriteLine(Output, L);
|
841 |
|
|
RxData := Data;
|
842 |
|
|
else
|
843 |
|
|
RxData := Data;
|
844 |
|
|
end if;
|
845 |
|
|
end procedure DMAComp;
|
846 |
|
|
|
847 |
|
|
-----------------------------------------------------------------------------
|
848 |
|
|
-- AMBA AHB write access
|
849 |
|
|
-----------------------------------------------------------------------------
|
850 |
|
|
procedure DMAWriteQuiet16(
|
851 |
|
|
constant Address: in Std_Logic_Vector(31 downto 0);
|
852 |
|
|
constant Data: in Std_Logic_Vector(15 downto 0);
|
853 |
|
|
signal HCLK: in Std_ULogic;
|
854 |
|
|
signal dmai: out dma_in_type;
|
855 |
|
|
signal dmao: in dma_out_type;
|
856 |
|
|
variable TP: inout Boolean;
|
857 |
|
|
constant InstancePath: in String := "DMAWrite16";
|
858 |
|
|
constant ScreenOutput: in Boolean := False;
|
859 |
|
|
constant cBack2Back: in Boolean := False;
|
860 |
|
|
constant Lock: in Boolean := False) is
|
861 |
|
|
begin
|
862 |
|
|
DMAWriteQuiet(Address, Data & Data, HCLK, dmai, dmao, TP,
|
863 |
|
|
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
|
864 |
|
|
end procedure DMAWriteQuiet16;
|
865 |
|
|
|
866 |
|
|
-----------------------------------------------------------------------------
|
867 |
|
|
-- AMBA AHB write access
|
868 |
|
|
-----------------------------------------------------------------------------
|
869 |
|
|
procedure DMAWrite16(
|
870 |
|
|
constant Address: in Std_Logic_Vector(31 downto 0);
|
871 |
|
|
constant Data: in Std_Logic_Vector(15 downto 0);
|
872 |
|
|
signal HCLK: in Std_ULogic;
|
873 |
|
|
signal dmai: out dma_in_type;
|
874 |
|
|
signal dmao: in dma_out_type;
|
875 |
|
|
variable TP: inout Boolean;
|
876 |
|
|
constant InstancePath: in String := "DMAWrite16";
|
877 |
|
|
constant ScreenOutput: in Boolean := False;
|
878 |
|
|
constant cBack2Back: in Boolean := False;
|
879 |
|
|
constant Lock: in Boolean := False) is
|
880 |
|
|
begin
|
881 |
|
|
DMAWrite(Address, Data & Data, HCLK, dmai, dmao, TP,
|
882 |
|
|
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
|
883 |
|
|
end procedure DMAWrite16;
|
884 |
|
|
|
885 |
|
|
-----------------------------------------------------------------------------
|
886 |
|
|
-- AMBA AHB read access
|
887 |
|
|
-----------------------------------------------------------------------------
|
888 |
|
|
procedure DMAQuiet16(
|
889 |
|
|
constant Address: in Std_Logic_Vector(31 downto 0);
|
890 |
|
|
variable Data: out Std_Logic_Vector(15 downto 0);
|
891 |
|
|
signal HCLK: in Std_ULogic;
|
892 |
|
|
signal dmai: out dma_in_type;
|
893 |
|
|
signal dmao: in dma_out_type;
|
894 |
|
|
variable TP: inout Boolean;
|
895 |
|
|
constant InstancePath: in String := "DMAQuiet16";
|
896 |
|
|
constant ScreenOutput: in Boolean := False;
|
897 |
|
|
constant cBack2Back: in Boolean := False;
|
898 |
|
|
constant Lock: in Boolean := False) is
|
899 |
|
|
variable Tmp: Std_Logic_Vector(31 downto 0);
|
900 |
|
|
begin
|
901 |
|
|
DMAQuiet(Address, Tmp, HCLK, dmai, dmao, TP,
|
902 |
|
|
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
|
903 |
|
|
if Address(1)='0' then
|
904 |
|
|
Data := Tmp(31 downto 16);
|
905 |
|
|
else
|
906 |
|
|
Data := Tmp(15 downto 0);
|
907 |
|
|
end if;
|
908 |
|
|
end procedure DMAQuiet16;
|
909 |
|
|
|
910 |
|
|
-----------------------------------------------------------------------------
|
911 |
|
|
-- AMBA AHB read access
|
912 |
|
|
-----------------------------------------------------------------------------
|
913 |
|
|
procedure DMARead16(
|
914 |
|
|
constant Address: in Std_Logic_Vector(31 downto 0);
|
915 |
|
|
variable Data: out Std_Logic_Vector(15 downto 0);
|
916 |
|
|
signal HCLK: in Std_ULogic;
|
917 |
|
|
signal dmai: out dma_in_type;
|
918 |
|
|
signal dmao: in dma_out_type;
|
919 |
|
|
variable TP: inout Boolean;
|
920 |
|
|
constant InstancePath: in String := "DMARead16";
|
921 |
|
|
constant ScreenOutput: in Boolean := True;
|
922 |
|
|
constant cBack2Back: in Boolean := False;
|
923 |
|
|
constant Lock: in Boolean := False) is
|
924 |
|
|
variable Tmp: Std_Logic_Vector(31 downto 0);
|
925 |
|
|
begin
|
926 |
|
|
DMARead(Address, Tmp, HCLK, dmai, dmao, TP,
|
927 |
|
|
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
|
928 |
|
|
if Address(1)='0' then
|
929 |
|
|
Data := Tmp(31 downto 16);
|
930 |
|
|
else
|
931 |
|
|
Data := Tmp(15 downto 0);
|
932 |
|
|
end if;
|
933 |
|
|
end procedure DMARead16;
|
934 |
|
|
|
935 |
|
|
-----------------------------------------------------------------------------
|
936 |
|
|
-- AMBA AHB read access
|
937 |
|
|
-----------------------------------------------------------------------------
|
938 |
|
|
procedure DMAComp16(
|
939 |
|
|
constant Address: in Std_Logic_Vector(31 downto 0);
|
940 |
|
|
constant CxData: in Std_Logic_Vector(15 downto 0);
|
941 |
|
|
variable RxData: out Std_Logic_Vector(15 downto 0);
|
942 |
|
|
signal HCLK: in Std_ULogic;
|
943 |
|
|
signal dmai: out dma_in_type;
|
944 |
|
|
signal dmao: in dma_out_type;
|
945 |
|
|
variable TP: inout Boolean;
|
946 |
|
|
constant InstancePath: in String := "DMAComp16";
|
947 |
|
|
constant ScreenOutput: in Boolean := False;
|
948 |
|
|
constant cBack2Back: in Boolean := False;
|
949 |
|
|
constant Lock: in Boolean := False) is
|
950 |
|
|
variable TmpRx: Std_Logic_Vector(31 downto 0);
|
951 |
|
|
variable TmpCx: Std_Logic_Vector(31 downto 0);
|
952 |
|
|
begin
|
953 |
|
|
if Address(1)='0' then
|
954 |
|
|
TmpCx := CxData & "----------------";
|
955 |
|
|
else
|
956 |
|
|
TmpCx := "----------------" & CxData;
|
957 |
|
|
end if;
|
958 |
|
|
DMAComp(Address, TmpCx, TmpRx, HCLK, dmai, dmao, TP,
|
959 |
|
|
InstancePath, ScreenOutput, cBack2Back, 16, Lock);
|
960 |
|
|
if Address(1)='0' then
|
961 |
|
|
RxData := TmpRx(31 downto 16);
|
962 |
|
|
else
|
963 |
|
|
RxData := TmpRx(15 downto 0);
|
964 |
|
|
end if;
|
965 |
|
|
end procedure DMAComp16;
|
966 |
|
|
|
967 |
|
|
|
968 |
|
|
-----------------------------------------------------------------------------
|
969 |
|
|
-- AMBA AHB write access
|
970 |
|
|
-----------------------------------------------------------------------------
|
971 |
|
|
procedure DMAWriteQuiet8(
|
972 |
|
|
constant Address: in Std_Logic_Vector(31 downto 0);
|
973 |
|
|
constant Data: in Std_Logic_Vector( 7 downto 0);
|
974 |
|
|
signal HCLK: in Std_ULogic;
|
975 |
|
|
signal dmai: out dma_in_type;
|
976 |
|
|
signal dmao: in dma_out_type;
|
977 |
|
|
variable TP: inout Boolean;
|
978 |
|
|
constant InstancePath: in String := "DMAWrite8";
|
979 |
|
|
constant ScreenOutput: in Boolean := False;
|
980 |
|
|
constant cBack2Back: in Boolean := False;
|
981 |
|
|
constant Lock: in Boolean := False) is
|
982 |
|
|
begin
|
983 |
|
|
DMAWriteQuiet(Address, Data & Data & Data & Data, HCLK, dmai, dmao, TP,
|
984 |
|
|
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
|
985 |
|
|
end procedure DMAWriteQuiet8;
|
986 |
|
|
|
987 |
|
|
-----------------------------------------------------------------------------
|
988 |
|
|
-- AMBA AHB write access
|
989 |
|
|
-----------------------------------------------------------------------------
|
990 |
|
|
procedure DMAWrite8(
|
991 |
|
|
constant Address: in Std_Logic_Vector(31 downto 0);
|
992 |
|
|
constant Data: in Std_Logic_Vector( 7 downto 0);
|
993 |
|
|
signal HCLK: in Std_ULogic;
|
994 |
|
|
signal dmai: out dma_in_type;
|
995 |
|
|
signal dmao: in dma_out_type;
|
996 |
|
|
variable TP: inout Boolean;
|
997 |
|
|
constant InstancePath: in String := "DMAWrite8";
|
998 |
|
|
constant ScreenOutput: in Boolean := False;
|
999 |
|
|
constant cBack2Back: in Boolean := False;
|
1000 |
|
|
constant Lock: in Boolean := False) is
|
1001 |
|
|
begin
|
1002 |
|
|
DMAWrite(Address, Data & Data & Data & Data, HCLK, dmai, dmao, TP,
|
1003 |
|
|
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
|
1004 |
|
|
end procedure DMAWrite8;
|
1005 |
|
|
|
1006 |
|
|
-----------------------------------------------------------------------------
|
1007 |
|
|
-- AMBA AHB read access
|
1008 |
|
|
-----------------------------------------------------------------------------
|
1009 |
|
|
procedure DMAQuiet8(
|
1010 |
|
|
constant Address: in Std_Logic_Vector(31 downto 0);
|
1011 |
|
|
variable Data: out Std_Logic_Vector( 7 downto 0);
|
1012 |
|
|
signal HCLK: in Std_ULogic;
|
1013 |
|
|
signal dmai: out dma_in_type;
|
1014 |
|
|
signal dmao: in dma_out_type;
|
1015 |
|
|
variable TP: inout Boolean;
|
1016 |
|
|
constant InstancePath: in String := "DMAQuiet8";
|
1017 |
|
|
constant ScreenOutput: in Boolean := False;
|
1018 |
|
|
constant cBack2Back: in Boolean := False;
|
1019 |
|
|
constant Lock: in Boolean := False) is
|
1020 |
|
|
variable Tmp: Std_Logic_Vector(31 downto 0);
|
1021 |
|
|
begin
|
1022 |
|
|
DMAQuiet(Address, Tmp, HCLK, dmai, dmao, TP,
|
1023 |
|
|
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
|
1024 |
|
|
if Address(1 downto 0)="00" then
|
1025 |
|
|
Data := Tmp(31 downto 24);
|
1026 |
|
|
elsif Address(1 downto 0)="01" then
|
1027 |
|
|
Data := Tmp(23 downto 16);
|
1028 |
|
|
elsif Address(1 downto 0)="10" then
|
1029 |
|
|
Data := Tmp(15 downto 8);
|
1030 |
|
|
else
|
1031 |
|
|
Data := Tmp( 7 downto 0);
|
1032 |
|
|
end if;
|
1033 |
|
|
end procedure DMAQuiet8;
|
1034 |
|
|
|
1035 |
|
|
-----------------------------------------------------------------------------
|
1036 |
|
|
-- AMBA AHB read access
|
1037 |
|
|
-----------------------------------------------------------------------------
|
1038 |
|
|
procedure DMARead8(
|
1039 |
|
|
constant Address: in Std_Logic_Vector(31 downto 0);
|
1040 |
|
|
variable Data: out Std_Logic_Vector( 7 downto 0);
|
1041 |
|
|
signal HCLK: in Std_ULogic;
|
1042 |
|
|
signal dmai: out dma_in_type;
|
1043 |
|
|
signal dmao: in dma_out_type;
|
1044 |
|
|
variable TP: inout Boolean;
|
1045 |
|
|
constant InstancePath: in String := "DMARead8";
|
1046 |
|
|
constant ScreenOutput: in Boolean := True;
|
1047 |
|
|
constant cBack2Back: in Boolean := False;
|
1048 |
|
|
constant Lock: in Boolean := False) is
|
1049 |
|
|
variable Tmp: Std_Logic_Vector(31 downto 0);
|
1050 |
|
|
begin
|
1051 |
|
|
DMARead(Address, Tmp, HCLK, dmai, dmao, TP,
|
1052 |
|
|
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
|
1053 |
|
|
if Address(1 downto 0)="00" then
|
1054 |
|
|
Data := Tmp(31 downto 24);
|
1055 |
|
|
elsif Address(1 downto 0)="01" then
|
1056 |
|
|
Data := Tmp(23 downto 16);
|
1057 |
|
|
elsif Address(1 downto 0)="10" then
|
1058 |
|
|
Data := Tmp(15 downto 8);
|
1059 |
|
|
else
|
1060 |
|
|
Data := Tmp( 7 downto 0);
|
1061 |
|
|
end if;
|
1062 |
|
|
end procedure DMARead8;
|
1063 |
|
|
|
1064 |
|
|
-----------------------------------------------------------------------------
|
1065 |
|
|
-- AMBA AHB read access
|
1066 |
|
|
-----------------------------------------------------------------------------
|
1067 |
|
|
procedure DMAComp8(
|
1068 |
|
|
constant Address: in Std_Logic_Vector(31 downto 0);
|
1069 |
|
|
constant CxData: in Std_Logic_Vector( 7 downto 0);
|
1070 |
|
|
variable RxData: out Std_Logic_Vector( 7 downto 0);
|
1071 |
|
|
signal HCLK: in Std_ULogic;
|
1072 |
|
|
signal dmai: out dma_in_type;
|
1073 |
|
|
signal dmao: in dma_out_type;
|
1074 |
|
|
variable TP: inout Boolean;
|
1075 |
|
|
constant InstancePath: in String := "DMAComp8";
|
1076 |
|
|
constant ScreenOutput: in Boolean := False;
|
1077 |
|
|
constant cBack2Back: in Boolean := False;
|
1078 |
|
|
constant Lock: in Boolean := False) is
|
1079 |
|
|
variable TmpRx: Std_Logic_Vector(31 downto 0);
|
1080 |
|
|
variable TmpCx: Std_Logic_Vector(31 downto 0);
|
1081 |
|
|
begin
|
1082 |
|
|
if Address(1 downto 0)="00" then
|
1083 |
|
|
TmpCx := CxData & "--------" & "--------" & "--------";
|
1084 |
|
|
elsif Address(1 downto 0)="01" then
|
1085 |
|
|
TmpCx := "--------" & CxData & "--------" & "--------";
|
1086 |
|
|
elsif Address(1 downto 0)="10" then
|
1087 |
|
|
TmpCx := "--------" & "--------" & CxData & "--------";
|
1088 |
|
|
else
|
1089 |
|
|
TmpCx := "--------" & "--------" & "--------" & CxData;
|
1090 |
|
|
end if;
|
1091 |
|
|
DMAComp(Address, TmpCx, TmpRx, HCLK, dmai, dmao, TP,
|
1092 |
|
|
InstancePath, ScreenOutput, cBack2Back, 8, Lock);
|
1093 |
|
|
if Address(1 downto 0)="00" then
|
1094 |
|
|
RxData := TmpRx(31 downto 24);
|
1095 |
|
|
elsif Address(1 downto 0)="01" then
|
1096 |
|
|
RxData := TmpRx(23 downto 16);
|
1097 |
|
|
elsif Address(1 downto 0)="10" then
|
1098 |
|
|
RxData := TmpRx(15 downto 8);
|
1099 |
|
|
else
|
1100 |
|
|
RxData := TmpRx( 7 downto 0);
|
1101 |
|
|
end if;
|
1102 |
|
|
end procedure DMAComp8;
|
1103 |
|
|
|
1104 |
|
|
-----------------------------------------------------------------------------
|
1105 |
|
|
-- AMBA AHB write access
|
1106 |
|
|
-----------------------------------------------------------------------------
|
1107 |
|
|
procedure DMAWriteQuietBurst(
|
1108 |
|
|
constant Address: in Std_Logic_Vector(31 downto 0);
|
1109 |
|
|
constant Data: in Data_Vector;
|
1110 |
|
|
signal HCLK: in Std_ULogic;
|
1111 |
|
|
signal dmai: out dma_in_type;
|
1112 |
|
|
signal dmao: in dma_out_type;
|
1113 |
|
|
variable TP: inout Boolean;
|
1114 |
|
|
constant InstancePath: in String := "DMAWrite";
|
1115 |
|
|
constant ScreenOutput: in Boolean := False;
|
1116 |
|
|
constant cBack2Back: in Boolean := False;
|
1117 |
|
|
constant Size: in Integer := 32;
|
1118 |
|
|
constant Beat: in Integer := 1;
|
1119 |
|
|
constant Lock: in Boolean := False) is
|
1120 |
|
|
variable L: Line;
|
1121 |
|
|
constant Count: Integer := Data'Length*WordSize/Size;
|
1122 |
|
|
variable GCount: Integer := Data'Length*WordSize/Size;
|
1123 |
|
|
variable DCount: Integer := 1;
|
1124 |
|
|
begin
|
1125 |
|
|
-- do not synchronise when a back-to-back access is requested
|
1126 |
|
|
if not cBack2Back then
|
1127 |
|
|
Synchronise(HCLK);
|
1128 |
|
|
end if;
|
1129 |
|
|
|
1130 |
|
|
dmai.Reset <= '0';
|
1131 |
|
|
dmai.Address <= Address;
|
1132 |
|
|
dmai.Data <= (others => '0');
|
1133 |
|
|
dmai.Request <= '1';
|
1134 |
|
|
dmai.Store <= '1';
|
1135 |
|
|
if Count > 1 then
|
1136 |
|
|
dmai.Burst <= '1';
|
1137 |
|
|
else
|
1138 |
|
|
dmai.Burst <= '0';
|
1139 |
|
|
end if;
|
1140 |
|
|
if Beat=1 then
|
1141 |
|
|
dmai.Beat <= HINCR;
|
1142 |
|
|
elsif Beat=4 then
|
1143 |
|
|
dmai.Beat <= HINCR4;
|
1144 |
|
|
elsif Beat=8 then
|
1145 |
|
|
dmai.Beat <= HINCR8;
|
1146 |
|
|
elsif Beat=16 then
|
1147 |
|
|
dmai.Beat <= HINCR16;
|
1148 |
|
|
else
|
1149 |
|
|
report "Unsupported beat"
|
1150 |
|
|
severity Failure;
|
1151 |
|
|
end if;
|
1152 |
|
|
if Size=32 then
|
1153 |
|
|
dmai.Size <= HSIZE32;
|
1154 |
|
|
elsif Size=16 then
|
1155 |
|
|
dmai.Size <= HSIZE16;
|
1156 |
|
|
elsif Size=8 then
|
1157 |
|
|
dmai.Size <= HSIZE8;
|
1158 |
|
|
else
|
1159 |
|
|
report "Unsupported data width"
|
1160 |
|
|
severity Failure;
|
1161 |
|
|
end if;
|
1162 |
|
|
|
1163 |
|
|
if Lock then
|
1164 |
|
|
dmai.Lock <= '1';
|
1165 |
|
|
else
|
1166 |
|
|
dmai.Lock <= '0';
|
1167 |
|
|
end if;
|
1168 |
|
|
|
1169 |
|
|
-- wait for first grant, indicating start of accesses
|
1170 |
|
|
wait for 1 ns;
|
1171 |
|
|
if dmao.Grant='0' then
|
1172 |
|
|
while dmao.Grant='0' loop
|
1173 |
|
|
Synchronise(HCLK);
|
1174 |
|
|
end loop;
|
1175 |
|
|
Synchronise(HCLK);
|
1176 |
|
|
else
|
1177 |
|
|
Synchronise(HCLK);
|
1178 |
|
|
end if;
|
1179 |
|
|
GCount := GCount-1;
|
1180 |
|
|
|
1181 |
|
|
-- first data
|
1182 |
|
|
if Size=32 then
|
1183 |
|
|
dmai.Data <= Data(0);
|
1184 |
|
|
elsif Size=16 then
|
1185 |
|
|
dmai.Data <= Data(0)(31 downto 16) & Data(0)(31 downto 16);
|
1186 |
|
|
elsif Size=8 then
|
1187 |
|
|
dmai.Data <= Data(0)(31 downto 24) & Data(0)(31 downto 24) &
|
1188 |
|
|
Data(0)(31 downto 24) & Data(0)(31 downto 24);
|
1189 |
|
|
end if;
|
1190 |
|
|
|
1191 |
|
|
loop
|
1192 |
|
|
-- remove request when all grants received
|
1193 |
|
|
if dmao.Grant='1' then
|
1194 |
|
|
if GCount=0 then
|
1195 |
|
|
dmai.Reset <= '0';
|
1196 |
|
|
dmai.Request <= '0';
|
1197 |
|
|
dmai.Store <= '0';
|
1198 |
|
|
dmai.Burst <= '0';
|
1199 |
|
|
else
|
1200 |
|
|
GCount := GCount-1;
|
1201 |
|
|
end if;
|
1202 |
|
|
end if;
|
1203 |
|
|
|
1204 |
|
|
Synchronise(HCLK, 0 ns);
|
1205 |
|
|
while dmao.Grant='0' and dmao.Ready='0' and dmao.OKAY='0' and dmao.Retry='0' and dmao.Fault='0' loop
|
1206 |
|
|
Synchronise(HCLK, 0 ns);
|
1207 |
|
|
end loop;
|
1208 |
|
|
|
1209 |
|
|
if dmao.Fault='1' then
|
1210 |
|
|
if ScreenOutput then
|
1211 |
|
|
Write (L, Now, Right, 15);
|
1212 |
|
|
Write (L, " : " & InstancePath);
|
1213 |
|
|
Write (L, String'(" : AHB write access, address: "));
|
1214 |
|
|
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
|
1215 |
|
|
Write (L, String'(" ERROR response "));
|
1216 |
|
|
WriteLine(Output, L);
|
1217 |
|
|
end if;
|
1218 |
|
|
TP := False;
|
1219 |
|
|
dmai.Reset <= '0';
|
1220 |
|
|
dmai.Address <= (others => '0');
|
1221 |
|
|
dmai.Data <= (others => '0');
|
1222 |
|
|
dmai.Request <= '0';
|
1223 |
|
|
dmai.Store <= '0';
|
1224 |
|
|
dmai.Burst <= '0';
|
1225 |
|
|
dmai.Beat <= (others => '0');
|
1226 |
|
|
dmai.Size <= (others => '0');
|
1227 |
|
|
Synchronise(HCLK, 0 ns);
|
1228 |
|
|
Synchronise(HCLK, 0 ns);
|
1229 |
|
|
exit;
|
1230 |
|
|
elsif dmao.OKAY='1' then
|
1231 |
|
|
-- for each OKAY, provide new data
|
1232 |
|
|
if DCount=Count then
|
1233 |
|
|
dmai.Address <= (others => '0');
|
1234 |
|
|
dmai.Beat <= (others => '0');
|
1235 |
|
|
dmai.Size <= (others => '0');
|
1236 |
|
|
Synchronise(HCLK, 0 ns);
|
1237 |
|
|
while dmao.Ready='0' loop
|
1238 |
|
|
Synchronise(HCLK, 0 ns);
|
1239 |
|
|
end loop;
|
1240 |
|
|
exit;
|
1241 |
|
|
else
|
1242 |
|
|
if Size=32 then
|
1243 |
|
|
dmai.Data <= Data(DCount);
|
1244 |
|
|
elsif Size=16 then
|
1245 |
|
|
dmai.Data <= Data(DCount/2)((31-16*(DCount mod 2)) downto (16-(16*(DCount mod 2)))) &
|
1246 |
|
|
Data(DCount/2)((31-16*(DCount mod 2)) downto (16-(16*(DCount mod 2))));
|
1247 |
|
|
elsif Size=8 then
|
1248 |
|
|
dmai.Data <= Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4)))) &
|
1249 |
|
|
Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4)))) &
|
1250 |
|
|
Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4)))) &
|
1251 |
|
|
Data(DCount/4)((31-8*(DCount mod 4)) downto (24-(8*(DCount mod 4))));
|
1252 |
|
|
end if;
|
1253 |
|
|
DCount := DCount+1;
|
1254 |
|
|
end if;
|
1255 |
|
|
end if;
|
1256 |
|
|
|
1257 |
|
|
|
1258 |
|
|
if dmao.Retry='1' then
|
1259 |
|
|
if ScreenOutput then
|
1260 |
|
|
Write (L, Now, Right, 15);
|
1261 |
|
|
Write (L, " : " & InstancePath);
|
1262 |
|
|
Write (L, String'(" : AHB write access, address: "));
|
1263 |
|
|
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
|
1264 |
|
|
Write (L, String'(" RETRY/SPLIT response "));
|
1265 |
|
|
WriteLine(Output, L);
|
1266 |
|
|
end if;
|
1267 |
|
|
end if;
|
1268 |
|
|
end loop;
|
1269 |
|
|
end procedure DMAWriteQuietBurst;
|
1270 |
|
|
|
1271 |
|
|
-----------------------------------------------------------------------------
|
1272 |
|
|
-- AMBA AHB write access
|
1273 |
|
|
-----------------------------------------------------------------------------
|
1274 |
|
|
procedure DMAWriteBurst(
|
1275 |
|
|
constant Address: in Std_Logic_Vector(31 downto 0);
|
1276 |
|
|
constant Data: in Data_Vector;
|
1277 |
|
|
signal HCLK: in Std_ULogic;
|
1278 |
|
|
signal dmai: out dma_in_type;
|
1279 |
|
|
signal dmao: in dma_out_type;
|
1280 |
|
|
variable TP: inout Boolean;
|
1281 |
|
|
constant InstancePath: in String := "DMAWrite";
|
1282 |
|
|
constant ScreenOutput: in Boolean := False;
|
1283 |
|
|
constant cBack2Back: in Boolean := False;
|
1284 |
|
|
constant Size: in Integer := 32;
|
1285 |
|
|
constant Beat: in Integer := 1;
|
1286 |
|
|
constant Lock: in Boolean := False) is
|
1287 |
|
|
variable OK: Boolean := True;
|
1288 |
|
|
variable L: Line;
|
1289 |
|
|
begin
|
1290 |
|
|
DMAWriteQuietBurst(Address, Data, HCLK, dmai, dmao, OK,
|
1291 |
|
|
InstancePath, ScreenOutput, cBack2Back, Size, Beat, Lock);
|
1292 |
|
|
if ScreenOutput and OK then
|
1293 |
|
|
for i in 0 to Data'Length-1 loop
|
1294 |
|
|
Write (L, Now, Right, 15);
|
1295 |
|
|
Write (L, " : " & InstancePath);
|
1296 |
|
|
Write (L, String'(" : AHB write access, address: "));
|
1297 |
|
|
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
|
1298 |
|
|
Write (L, String'(" : data: "));
|
1299 |
|
|
HWrite(L, Data(i));
|
1300 |
|
|
WriteLine(Output, L);
|
1301 |
|
|
end loop;
|
1302 |
|
|
elsif not OK then
|
1303 |
|
|
Write (L, Now, Right, 15);
|
1304 |
|
|
Write (L, " : " & InstancePath);
|
1305 |
|
|
Write (L, String'(" : AHB write access, address: "));
|
1306 |
|
|
HWrite(L, Address);
|
1307 |
|
|
Write (L, String'(" : ## Failed ##"));
|
1308 |
|
|
WriteLine(Output, L);
|
1309 |
|
|
TP := False;
|
1310 |
|
|
end if;
|
1311 |
|
|
end procedure DMAWriteBurst;
|
1312 |
|
|
|
1313 |
|
|
-----------------------------------------------------------------------------
|
1314 |
|
|
-- AMBA AHB read access
|
1315 |
|
|
-----------------------------------------------------------------------------
|
1316 |
|
|
procedure DMAQuietBurst(
|
1317 |
|
|
constant Address: in Std_Logic_Vector(31 downto 0);
|
1318 |
|
|
variable Data: out Data_Vector;
|
1319 |
|
|
signal HCLK: in Std_ULogic;
|
1320 |
|
|
signal dmai: out dma_in_type;
|
1321 |
|
|
signal dmao: in dma_out_type;
|
1322 |
|
|
variable TP: inout Boolean;
|
1323 |
|
|
constant InstancePath: in String := "DMAQuiet";
|
1324 |
|
|
constant ScreenOutput: in Boolean := False;
|
1325 |
|
|
constant cBack2Back: in Boolean := False;
|
1326 |
|
|
constant Size: in Integer := 32;
|
1327 |
|
|
constant Beat: in Integer := 1;
|
1328 |
|
|
constant Lock: in Boolean := False) is
|
1329 |
|
|
variable L: Line;
|
1330 |
|
|
constant Count: Integer := Data'Length*WordSize/Size;
|
1331 |
|
|
variable GCount: Integer := Data'Length*WordSize/Size;
|
1332 |
|
|
variable DCount: Integer := 1;
|
1333 |
|
|
variable DataPart: Integer := 0;
|
1334 |
|
|
begin
|
1335 |
|
|
-- do not Synchronise when a back-to-back access is requested
|
1336 |
|
|
if not cBack2Back then
|
1337 |
|
|
Synchronise(HCLK);
|
1338 |
|
|
end if;
|
1339 |
|
|
|
1340 |
|
|
dmai.Reset <= '0';
|
1341 |
|
|
dmai.Address <= Address;
|
1342 |
|
|
dmai.Data <= (others => '0');
|
1343 |
|
|
dmai.Request <= '1';
|
1344 |
|
|
dmai.Store <= '0';
|
1345 |
|
|
if Count > 1 then
|
1346 |
|
|
dmai.Burst <= '1';
|
1347 |
|
|
else
|
1348 |
|
|
dmai.Burst <= '0';
|
1349 |
|
|
end if;
|
1350 |
|
|
if Beat=1 then
|
1351 |
|
|
dmai.Beat <= HINCR;
|
1352 |
|
|
elsif Beat=4 then
|
1353 |
|
|
dmai.Beat <= HINCR4;
|
1354 |
|
|
elsif Beat=8 then
|
1355 |
|
|
dmai.Beat <= HINCR8;
|
1356 |
|
|
elsif Beat=16 then
|
1357 |
|
|
dmai.Beat <= HINCR16;
|
1358 |
|
|
else
|
1359 |
|
|
report "Unsupported beat"
|
1360 |
|
|
severity Failure;
|
1361 |
|
|
end if;
|
1362 |
|
|
if Size=32 then
|
1363 |
|
|
dmai.Size <= HSIZE32;
|
1364 |
|
|
elsif Size=16 then
|
1365 |
|
|
dmai.Size <= HSIZE16;
|
1366 |
|
|
if Address(1 downto 0) = "00" then
|
1367 |
|
|
DataPart := 0;
|
1368 |
|
|
else
|
1369 |
|
|
DataPart := 1;
|
1370 |
|
|
end if;
|
1371 |
|
|
elsif Size=8 then
|
1372 |
|
|
dmai.Size <= HSIZE8;
|
1373 |
|
|
if Address(1 downto 0) = "00" then
|
1374 |
|
|
DataPart := 0;
|
1375 |
|
|
elsif Address(1 downto 0) = "01" then
|
1376 |
|
|
DataPart := 1;
|
1377 |
|
|
elsif Address(1 downto 0) = "10" then
|
1378 |
|
|
DataPart := 2;
|
1379 |
|
|
else
|
1380 |
|
|
DataPart := 3;
|
1381 |
|
|
end if;
|
1382 |
|
|
else
|
1383 |
|
|
report "Unsupported data width"
|
1384 |
|
|
severity Failure;
|
1385 |
|
|
end if;
|
1386 |
|
|
|
1387 |
|
|
if Lock then
|
1388 |
|
|
dmai.Lock <= '1';
|
1389 |
|
|
else
|
1390 |
|
|
dmai.Lock <= '0';
|
1391 |
|
|
end if;
|
1392 |
|
|
|
1393 |
|
|
|
1394 |
|
|
-- wait for first grant, indicating start of accesses
|
1395 |
|
|
wait for 1 ns;
|
1396 |
|
|
if dmao.Grant='0' then
|
1397 |
|
|
while dmao.Grant='0' loop
|
1398 |
|
|
Synchronise(HCLK);
|
1399 |
|
|
end loop;
|
1400 |
|
|
Synchronise(HCLK);
|
1401 |
|
|
else
|
1402 |
|
|
Synchronise(HCLK);
|
1403 |
|
|
end if;
|
1404 |
|
|
GCount := GCount-1;
|
1405 |
|
|
|
1406 |
|
|
loop
|
1407 |
|
|
-- remove request when all grants received
|
1408 |
|
|
if dmao.Grant='1' then
|
1409 |
|
|
if GCount=0 then
|
1410 |
|
|
dmai.Reset <= '0';
|
1411 |
|
|
dmai.Data <= (others => '0');
|
1412 |
|
|
dmai.Request <= '0';
|
1413 |
|
|
dmai.Store <= '0';
|
1414 |
|
|
dmai.Burst <= '0';
|
1415 |
|
|
else
|
1416 |
|
|
GCount := GCount-1;
|
1417 |
|
|
end if;
|
1418 |
|
|
end if;
|
1419 |
|
|
|
1420 |
|
|
Synchronise(HCLK);
|
1421 |
|
|
while dmao.Grant='0' and dmao.Ready='0' and dmao.Retry='0' and dmao.Fault='0' loop
|
1422 |
|
|
Synchronise(HCLK);
|
1423 |
|
|
end loop;
|
1424 |
|
|
|
1425 |
|
|
if dmao.Fault='1' then
|
1426 |
|
|
if ScreenOutput then
|
1427 |
|
|
Write (L, Now, Right, 15);
|
1428 |
|
|
Write (L, " : " & InstancePath);
|
1429 |
|
|
Write (L, String'(" : AHB read access, address: "));
|
1430 |
|
|
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
|
1431 |
|
|
Write (L, String'(" ERROR response"));
|
1432 |
|
|
WriteLine(Output, L);
|
1433 |
|
|
end if;
|
1434 |
|
|
TP := False;
|
1435 |
|
|
dmai.Reset <= '0';
|
1436 |
|
|
dmai.Address <= (others => '0');
|
1437 |
|
|
dmai.Data <= (others => '0');
|
1438 |
|
|
dmai.Request <= '0';
|
1439 |
|
|
dmai.Store <= '0';
|
1440 |
|
|
dmai.Burst <= '0';
|
1441 |
|
|
dmai.Beat <= (others => '0');
|
1442 |
|
|
dmai.Size <= (others => '0');
|
1443 |
|
|
Synchronise(HCLK);
|
1444 |
|
|
Synchronise(HCLK);
|
1445 |
|
|
exit;
|
1446 |
|
|
elsif dmao.Ready='1' then
|
1447 |
|
|
-- for each READY, store data
|
1448 |
|
|
if Size=32 then
|
1449 |
|
|
Data(DCount-1) := dmao.Data;
|
1450 |
|
|
elsif Size=16 then
|
1451 |
|
|
Data((DCount-1)/2)((31-16*((DCount-1) mod 2)) downto (16-(16*((DCount-1) mod 2)))) :=
|
1452 |
|
|
dmao.Data((31-16*DataPart) downto (16-16*DataPart));
|
1453 |
|
|
DataPart := (DataPart + 1) mod 2;
|
1454 |
|
|
elsif Size=8 then
|
1455 |
|
|
Data((DCount-1)/4)((31-8*((DCount-1) mod 4)) downto (24-(8*((DCount-1) mod 4)))) :=
|
1456 |
|
|
dmao.Data((31-8*DataPart) downto (24-8*DataPart));
|
1457 |
|
|
DataPart := (DataPart + 1) mod 4;
|
1458 |
|
|
end if;
|
1459 |
|
|
|
1460 |
|
|
if DCount=Count then
|
1461 |
|
|
dmai.Address <= (others => '0');
|
1462 |
|
|
dmai.Beat <= (others => '0');
|
1463 |
|
|
dmai.Size <= (others => '0');
|
1464 |
|
|
exit;
|
1465 |
|
|
else
|
1466 |
|
|
DCount := DCount+1;
|
1467 |
|
|
end if;
|
1468 |
|
|
end if;
|
1469 |
|
|
|
1470 |
|
|
if dmao.Retry='1' then
|
1471 |
|
|
if ScreenOutput then
|
1472 |
|
|
Write (L, Now, Right, 15);
|
1473 |
|
|
Write (L, " : " & InstancePath);
|
1474 |
|
|
Write (L, String'(" : AHB read access, address: "));
|
1475 |
|
|
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+(DCount-1)*Beat*Size/8, 32));
|
1476 |
|
|
Write (L, String'(" RETRY/SPLIT response "));
|
1477 |
|
|
WriteLine(Output, L);
|
1478 |
|
|
end if;
|
1479 |
|
|
end if;
|
1480 |
|
|
end loop;
|
1481 |
|
|
end procedure DMAQuietBurst;
|
1482 |
|
|
|
1483 |
|
|
|
1484 |
|
|
-----------------------------------------------------------------------------
|
1485 |
|
|
-- AMBA AHB read access
|
1486 |
|
|
-----------------------------------------------------------------------------
|
1487 |
|
|
procedure DMAReadBurst(
|
1488 |
|
|
constant Address: in Std_Logic_Vector(31 downto 0);
|
1489 |
|
|
variable Data: out Data_Vector;
|
1490 |
|
|
signal HCLK: in Std_ULogic;
|
1491 |
|
|
signal dmai: out dma_in_type;
|
1492 |
|
|
signal dmao: in dma_out_type;
|
1493 |
|
|
variable TP: inout Boolean;
|
1494 |
|
|
constant InstancePath: in String := "DMARead";
|
1495 |
|
|
constant ScreenOutput: in Boolean := True;
|
1496 |
|
|
constant cBack2Back: in Boolean := False;
|
1497 |
|
|
constant Size: in Integer := 32;
|
1498 |
|
|
constant Beat: in Integer := 1;
|
1499 |
|
|
constant Lock: in Boolean := False) is
|
1500 |
|
|
variable OK: Boolean := True;
|
1501 |
|
|
variable L: Line;
|
1502 |
|
|
variable Temp: Data_Vector(0 to Data'Length-1);
|
1503 |
|
|
begin
|
1504 |
|
|
DMAQuietBurst(Address, Temp, HCLK, dmai, dmao, OK,
|
1505 |
|
|
InstancePath, ScreenOutput, cBack2Back, Size, Beat, Lock);
|
1506 |
|
|
if ScreenOutput and OK then
|
1507 |
|
|
Data := Temp;
|
1508 |
|
|
for i in 0 to Data'Length-1 loop
|
1509 |
|
|
Write (L, Now, Right, 15);
|
1510 |
|
|
Write (L, " : " & InstancePath);
|
1511 |
|
|
Write (L, String'(" : AHB read access, address: "));
|
1512 |
|
|
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
|
1513 |
|
|
Write (L, String'(" : data: "));
|
1514 |
|
|
HWrite(L, Temp(i));
|
1515 |
|
|
WriteLine(Output, L);
|
1516 |
|
|
end loop;
|
1517 |
|
|
elsif OK then
|
1518 |
|
|
Data := Temp;
|
1519 |
|
|
else
|
1520 |
|
|
Write (L, Now, Right, 15);
|
1521 |
|
|
Write (L, " : " & InstancePath);
|
1522 |
|
|
Write (L, String'(" : AHB read access, address: "));
|
1523 |
|
|
HWrite(L, Address);
|
1524 |
|
|
Write (L, String'(" : ## Failed ##"));
|
1525 |
|
|
WriteLine(Output, L);
|
1526 |
|
|
Temp := (others => (others => '-'));
|
1527 |
|
|
Data := Temp;
|
1528 |
|
|
TP := False;
|
1529 |
|
|
end if;
|
1530 |
|
|
end procedure DMAReadBurst;
|
1531 |
|
|
|
1532 |
|
|
|
1533 |
|
|
-----------------------------------------------------------------------------
|
1534 |
|
|
-- AMBA AHB read access
|
1535 |
|
|
-----------------------------------------------------------------------------
|
1536 |
|
|
procedure DMACompBurst(
|
1537 |
|
|
constant Address: in Std_Logic_Vector(31 downto 0);
|
1538 |
|
|
variable CxData: in Data_Vector;
|
1539 |
|
|
variable RxData: out Data_Vector;
|
1540 |
|
|
signal HCLK: in Std_ULogic;
|
1541 |
|
|
signal dmai: out dma_in_type;
|
1542 |
|
|
signal dmao: in dma_out_type;
|
1543 |
|
|
variable TP: inout Boolean;
|
1544 |
|
|
constant InstancePath: in String := "DMAComp";
|
1545 |
|
|
constant ScreenOutput: in Boolean := False;
|
1546 |
|
|
constant cBack2Back: in Boolean := False;
|
1547 |
|
|
constant Size: in Integer := 32;
|
1548 |
|
|
constant Beat: in Integer := 1;
|
1549 |
|
|
constant Lock: in Boolean := False) is
|
1550 |
|
|
variable OK: Boolean := True;
|
1551 |
|
|
variable L: Line;
|
1552 |
|
|
variable Data: Data_Vector(0 to CxData'Length-1);
|
1553 |
|
|
begin
|
1554 |
|
|
DMAQuietBurst(Address, Data, HCLK, dmai, dmao, OK,
|
1555 |
|
|
InstancePath, ScreenOutput, cBack2Back, Size, Beat, Lock);
|
1556 |
|
|
if not OK then
|
1557 |
|
|
Write (L, Now, Right, 15);
|
1558 |
|
|
Write (L, " : " & InstancePath);
|
1559 |
|
|
Write (L, String'(" : AHB read access, address: "));
|
1560 |
|
|
HWrite(L, Address);
|
1561 |
|
|
Write (L, String'(" : ## Failed ##"));
|
1562 |
|
|
WriteLine(Output, L);
|
1563 |
|
|
TP := False;
|
1564 |
|
|
Data := (others => (others => '-'));
|
1565 |
|
|
RxData := Data;
|
1566 |
|
|
else
|
1567 |
|
|
for i in 0 to Data'Length-1 loop
|
1568 |
|
|
if not Compare(Data(i), CxData(i)) then
|
1569 |
|
|
Write(L, Now, Right, 15);
|
1570 |
|
|
Write(L, " : " & InstancePath);
|
1571 |
|
|
Write(L, String'(" : AHB read access, address: "));
|
1572 |
|
|
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
|
1573 |
|
|
Write(L, String'(" : data: "));
|
1574 |
|
|
HWrite(L, Data(i));
|
1575 |
|
|
Write(L, String'(" : expected: "));
|
1576 |
|
|
HWrite(L, CxData(i));
|
1577 |
|
|
Write(L, String'(" # Error #"));
|
1578 |
|
|
WriteLine(Output, L);
|
1579 |
|
|
TP := False;
|
1580 |
|
|
elsif ScreenOutput then
|
1581 |
|
|
Write(L, Now, Right, 15);
|
1582 |
|
|
Write(L, " : " & InstancePath);
|
1583 |
|
|
Write(L, String'(" : AHB read access, address: "));
|
1584 |
|
|
HWrite(L, Conv_Std_Logic_Vector(Conv_Integer(Address)+i*Beat*Size/8, 32));
|
1585 |
|
|
Write(L, String'(" : data: "));
|
1586 |
|
|
HWrite(L, Data(i));
|
1587 |
|
|
WriteLine(Output, L);
|
1588 |
|
|
end if;
|
1589 |
|
|
end loop;
|
1590 |
|
|
RxData := Data;
|
1591 |
|
|
end if;
|
1592 |
|
|
end procedure DMACompBurst;
|
1593 |
|
|
|
1594 |
|
|
end package body DMA2AHB_TestPackage; --======================================--
|