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dimamali |
---------------------------------------------------------------------
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---- ----
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---- Generic Up/Down counter (ripple carry architecture) ----
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---- ----
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---- Author: Richard Herveille ----
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---- richard@asics.ws ----
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---- www.asics.ws ----
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---- ----
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---------------------------------------------------------------------
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---- ----
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---- Copyright (C) 2001, 2002 Richard Herveille ----
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---- richard@asics.ws ----
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---- ----
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---- This source file may be used and distributed without ----
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---- restriction provided that this copyright statement is not ----
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---- removed from the file and that any derivative work contains ----
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---- the original copyright notice and the associated disclaimer.----
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---- ----
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---- THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ----
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---- EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ----
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---- TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ----
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---- FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ----
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---- OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ----
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---- INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ----
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---- (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ----
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---- GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ----
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---- BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ----
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---- LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ----
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---- (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ----
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---- OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ----
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---- POSSIBILITY OF SUCH DAMAGE. ----
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---- ----
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---------------------------------------------------------------------
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--
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-- CVS Log
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--
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-- $Id: ud_cnt.vhd,v 1.1 2002/03/01 03:49:03 rherveille Exp $
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--
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-- $Date: 2002/03/01 03:49:03 $
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-- $Revision: 1.1 $
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-- $Author: rherveille $
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-- $Locker: $
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-- $State: Exp $
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--
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-- Change History:
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-- $Log: ud_cnt.vhd,v $
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-- Revision 1.1 2002/03/01 03:49:03 rherveille
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-- Changed internal counter libraries.
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-- Split counter.vhd into separate files.
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-- Core is in same state as Verilog version now.
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--
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library ieee;
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use ieee.std_logic_1164.all;
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--use ieee.std_logic_arith.all;
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library grlib;
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use grlib.stdlib.all;
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entity ud_cnt is
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generic(
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SIZE : natural := 8;
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RESD : natural := 0
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);
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port(
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clk : in std_logic; -- master clock
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nReset : in std_logic := '1'; -- asynchronous active low reset
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rst : in std_logic := '0'; -- synchronous active high reset
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cnt_en : in std_logic := '1'; -- count enable
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ud : in std_logic := '0'; -- up / not down
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nld : in std_logic := '1'; -- synchronous active low load
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d : in std_logic_vector(SIZE -1 downto 0); -- load counter value
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q : out std_logic_vector(SIZE -1 downto 0); -- current counter value
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rci : in std_logic := '1'; -- carry input
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rco : out std_logic -- carry output
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);
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end entity ud_cnt;
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architecture structural of ud_cnt is
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signal Qi : std_logic_vector(SIZE -1 downto 0);
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signal val : std_logic_vector(SIZE downto 0);
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begin
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val <= ( ('0' & Qi) + rci) when (ud = '1') else ( ('0' & Qi) - rci);
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regs: process(clk, nReset)
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begin
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if (nReset = '0') then
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Qi <= conv_std_logic_vector(RESD, SIZE);
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elsif (clk'event and clk = '1') then
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if (rst = '1') then
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Qi <= conv_std_logic_vector(RESD, SIZE);
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else
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if (nld = '0') then
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Qi <= D;
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elsif (cnt_en = '1') then
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Qi <= val(SIZE -1 downto 0);
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end if;
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end if;
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end if;
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end process regs;
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-- assign outputs
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Q <= Qi;
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rco <= val(SIZE);
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end architecture structural;
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