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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: various
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-- File: mem_axcelerator_gen.vhd
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-- Author: Jiri Gaisler Gaisler Research
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-- Description: Memory generators for Actel AX rams
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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-- pragma translate_off
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library axcelerator;
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use axcelerator.RAM64K36;
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-- pragma translate_on
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entity axcel_ssram is
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generic (abits : integer := 16; dbits : integer := 36);
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port (
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wa, ra : in std_logic_vector(15 downto 0);
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wclk, rclk : in std_ulogic;
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di : in std_logic_vector(dbits -1 downto 0);
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do : out std_logic_vector(dbits -1 downto 0);
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width : in std_logic_vector(2 downto 0);
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ren, wen : in std_ulogic
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);
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end;
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architecture rtl of axcel_ssram is
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component RAM64K36
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port(
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WRAD0, WRAD1, WRAD2, WRAD3, WRAD4, WRAD5, WRAD6, WRAD7, WRAD8, WRAD9, WRAD10,
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WRAD11, WRAD12, WRAD13, WRAD14, WRAD15, WD0, WD1, WD2, WD3, WD4, WD5, WD6,
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WD7, WD8, WD9, WD10, WD11, WD12, WD13, WD14, WD15, WD16, WD17, WD18, WD19,
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WD20, WD21, WD22, WD23, WD24, WD25, WD26, WD27, WD28, WD29, WD30, WD31, WD32,
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WD33, WD34, WD35, WEN, DEPTH0, DEPTH1, DEPTH2, DEPTH3, WW0, WW1, WW2, WCLK,
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RDAD0, RDAD1, RDAD2, RDAD3, RDAD4, RDAD5, RDAD6, RDAD7, RDAD8, RDAD9, RDAD10,
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RDAD11, RDAD12, RDAD13, RDAD14, RDAD15, REN, RW0, RW1, RW2, RCLK : in std_logic;
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RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7, RD8, RD9, RD10, RD11, RD12, RD13,
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RD14, RD15, RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23, RD24, RD25, RD26,
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RD27, RD28, RD29, RD30, RD31, RD32, RD33, RD34, RD35 : out std_logic);
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end component;
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signal gnd : std_ulogic;
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signal depth : std_logic_vector(4 downto 0);
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signal d, q : std_logic_vector(36 downto 0);
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begin
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depth <= "00000";
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do <= q(dbits-1 downto 0);
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d(dbits-1 downto 0) <= di;
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d(36 downto dbits) <= (others => '0');
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u0 : RAM64K36
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port map (
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WRAD0 => wa(0), WRAD1 => wa(1), WRAD2 => wa(2), WRAD3 => wa(3),
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WRAD4 => wa(4), WRAD5 => wa(5), WRAD6 => wa(6), WRAD7 => wa(7),
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WRAD8 => wa(8), WRAD9 => wa(9), WRAD10 => wa(10), WRAD11 => wa(11),
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WRAD12 => wa(12), WRAD13 => wa(13), WRAD14 => wa(14), WRAD15 => wa(15),
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WD0 => d(0), WD1 => d(1), WD2 => d(2), WD3 => d(3), WD4 => d(4),
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WD5 => d(5), WD6 => d(6), WD7 => d(7), WD8 => d(8), WD9 => d(9),
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WD10 => d(10), WD11 => d(11), WD12 => d(12), WD13 => d(13), WD14 => d(14),
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WD15 => d(15), WD16 => d(16), WD17 => d(17), WD18 => d(18), WD19 => d(19),
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WD20 => d(20), WD21 => d(21), WD22 => d(22), WD23 => d(23), WD24 => d(24),
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WD25 => d(25), WD26 => d(26), WD27 => d(27), WD28 => d(28), WD29 => d(29),
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WD30 => d(30), WD31 => d(31), WD32 => d(32), WD33 => d(33), WD34 => d(34),
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WD35 => d(35), WEN => wen, DEPTH0 => depth(0),
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DEPTH1 => depth(1), DEPTH2 => depth(2), DEPTH3 => depth(3),
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WW0 => width(0), WW1 => width(1), WW2 => width(2), WCLK => wclk,
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RDAD0 => ra(0), RDAD1 => ra(1), RDAD2 => ra(2), RDAD3 => ra(3),
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RDAD4 => ra(4), RDAD5 => ra(5), RDAD6 => ra(6), RDAD7 => ra(7),
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RDAD8 => ra(8), RDAD9 => ra(9), RDAD10 => ra(10), RDAD11 => ra(11),
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RDAD12 => ra(12), RDAD13 => ra(13), RDAD14 => ra(14), RDAD15 => ra(15),
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REN => ren, RW0 => width(0), RW1 => width(1), RW2 => width(2),
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RCLK => rclk,
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RD0 => q(0), RD1 => q(1), RD2 => q(2), RD3 => q(3), RD4 => q(4),
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RD5 => q(5), RD6 => q(6), RD7 => q(7), RD8 => q(8), RD9 => q(9),
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RD10 => q(10), RD11 => q(11), RD12 => q(12), RD13 => q(13), RD14 => q(14),
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RD15 => q(15), RD16 => q(16), RD17 => q(17), RD18 => q(18), RD19 => q(19),
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RD20 => q(20), RD21 => q(21), RD22 => q(22), RD23 => q(23), RD24 => q(24),
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RD25 => q(25), RD26 => q(26), RD27 => q(27), RD28 => q(28), RD29 => q(29),
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RD30 => q(30), RD31 => q(31), RD32 => q(32), RD33 => q(33), RD34 => q(34),
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RD35 => q(35));
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end;
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library ieee;
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use ieee.std_logic_1164.all;
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library techmap;
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entity axcel_syncram_2p is
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generic ( abits : integer := 10; dbits : integer := 8 );
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port (
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rclk : in std_ulogic;
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rena : in std_ulogic;
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raddr : in std_logic_vector (abits -1 downto 0);
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dout : out std_logic_vector (dbits -1 downto 0);
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wclk : in std_ulogic;
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waddr : in std_logic_vector (abits -1 downto 0);
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din : in std_logic_vector (dbits -1 downto 0);
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write : in std_ulogic);
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end;
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architecture rtl of axcel_syncram_2p is
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component axcel_ssram
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generic (abits : integer := 16; dbits : integer := 36);
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port (
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wa, ra : in std_logic_vector(15 downto 0);
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wclk, rclk : in std_ulogic;
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di : in std_logic_vector(dbits -1 downto 0);
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do : out std_logic_vector(dbits -1 downto 0);
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width : in std_logic_vector(2 downto 0);
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ren, wen : in std_ulogic
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);
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end component;
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type dwtype is array (1 to 24) of integer;
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constant dwmap : dwtype := (36, 36, 36, 36, 36, 36, 36, 18, 9, 4, 2, others => 1);
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constant xbits : integer := dwmap(abits);
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constant dw : integer := dbits + 36;
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signal wen, gnd : std_ulogic;
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signal ra, wa : std_logic_vector(31 downto 0);
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signal d, q : std_logic_vector(dw downto 0);
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signal ren : std_ulogic;
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signal width : std_logic_vector(2 downto 0);
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constant READFAST : std_ulogic := '0';
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begin
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width <= "101" when abits <= 7 else
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"100" when abits = 8 else
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"011" when abits = 9 else
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"010" when abits = 10 else
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"001" when abits = 11 else
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"000";
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wen <= write; ren <= rena or READFAST; gnd <= '0';
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ra(31 downto abits) <= (others =>'0'); wa(31 downto abits) <= (others =>'0');
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ra(abits-1 downto 0) <= raddr(abits-1 downto 0);
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wa(abits-1 downto 0) <= waddr(abits-1 downto 0);
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d(dw downto dbits) <= (others =>'0');
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d(dbits-1 downto 0) <= din(dbits-1 downto 0);
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dout <= q(dbits-1 downto 0);
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a7 : if abits <= 7 generate
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agen : for i in 0 to (dbits-1)/xbits generate
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u0 : axcel_ssram
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generic map (abits => 7, dbits => xbits)
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port map (ra => ra(15 downto 0), wa => wa(15 downto 0),
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di => d(xbits*(i+1)-1 downto xbits*i), wen => wen, width => width,
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wclk => wclk, ren => ren, rclk => rclk,
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do => q(xbits*(i+1)-1 downto xbits*i));
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end generate;
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end generate;
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a8to12 : if (abits > 7) and (abits <= 12) generate
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agen : for i in 0 to (dbits-1)/xbits generate
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u0 : axcel_ssram
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generic map (abits => abits, dbits => xbits)
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port map (ra => ra(15 downto 0), wa => wa(15 downto 0),
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di => d(xbits*(i+1)-1 downto xbits*i), wen => wen, width => width,
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wclk => wclk, ren => ren, rclk => rclk,
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do => q(xbits*(i+1)-1 downto xbits*i));
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end generate;
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end generate;
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-- pragma translate_off
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a_to_high : if abits > 12 generate
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x : process
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begin
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assert false
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report "Address depth larger than 12 not supported for AX rams"
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severity failure;
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wait;
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end process;
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end generate;
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-- pragma translate_on
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end;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity axcel_syncram is
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generic ( abits : integer := 10; dbits : integer := 8 );
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port (
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clk : in std_ulogic;
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address : in std_logic_vector((abits -1) downto 0);
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datain : in std_logic_vector((dbits -1) downto 0);
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dataout : out std_logic_vector((dbits -1) downto 0);
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enable : in std_ulogic;
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write : in std_ulogic
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);
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end;
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architecture rtl of axcel_syncram is
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component axcel_syncram_2p
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generic ( abits : integer := 10; dbits : integer := 8 );
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port (
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rclk : in std_ulogic;
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rena : in std_ulogic;
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raddr : in std_logic_vector (abits -1 downto 0);
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dout : out std_logic_vector (dbits -1 downto 0);
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wclk : in std_ulogic;
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waddr : in std_logic_vector (abits -1 downto 0);
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din : in std_logic_vector (dbits -1 downto 0);
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write : in std_ulogic);
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end component;
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component axcel_ssram
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generic (abits : integer := 16; dbits : integer := 36);
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port (
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wa, ra : in std_logic_vector(15 downto 0);
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wclk, rclk : in std_ulogic;
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di : in std_logic_vector(dbits -1 downto 0);
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do : out std_logic_vector(dbits -1 downto 0);
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width : in std_logic_vector(2 downto 0);
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ren, wen : in std_ulogic
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);
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end component;
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type d_type is array (0 to 3) of std_logic_vector(35 downto 0);
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signal wen : std_logic_vector(3 downto 0);
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signal q : d_type;
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signal addr : std_logic_vector(15 downto 0);
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signal addrreg : std_logic_vector(1 downto 0);
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begin
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a : if not ((abits = 10 or abits = 11) and dbits = 36) generate
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u0 : axcel_syncram_2p generic map (abits, dbits)
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port map (clk, enable, address, dataout, clk, address, datain, write);
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end generate;
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-- Special case for 4 or 8 KB cache with FT: 36x1024 or 2048: 2 or 4 banks of 4*9*512
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a10to11d36 : if (abits = 10 or abits = 11) and dbits = 36 generate
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addr_reg : process (clk)
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begin
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if rising_edge(clk) then addrreg(abits-10 downto 0) <= address(abits-1 downto 9); end if;
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end process;
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addr(15 downto 9) <= (others => '0');
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addr(8 downto 0) <= address(8 downto 0);
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decode : process (address, write)
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variable vwen : std_logic_vector(3 downto 0);
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begin
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vwen := (others => '0');
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if write = '1' then
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vwen( to_integer(unsigned(address(abits-1 downto 9))) ) := '1';
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end if;
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wen <= vwen;
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end process;
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loop0 : for b in 0 to 2*(abits-9)-1 generate
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agen0 : for i in 0 to 3 generate
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u0 : axcel_ssram
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generic map (abits => 9, dbits => 9)
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port map (ra => addr, wa => addr,
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di => datain(9*(i+1)-1 downto 9*i), wen => wen(b), width => "011",
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wclk => clk, ren => enable, rclk => clk,
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do => q(b)(9*(i+1)-1 downto 9*i));
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end generate;
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end generate;
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dout10: if abits = 10 generate
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dataout <= q(0) when addrreg(0)='0' else q(1);
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end generate;
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dout11: if abits = 11 generate
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dataout <= q(0) when addrreg(1 downto 0)="00" else q(1) when addrreg(1 downto 0)="01" else
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q(2) when addrreg(1 downto 0)="10" else q(3);
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end generate;
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end generate;
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end;
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