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------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: libddr
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-- File: libddr.vhd
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-- Author: David Lindh, Jiri Gaisler - Gaisler Research
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-- Description: DDR input/output registers
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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library techmap;
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use techmap.gencomp.all;
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package allddr is
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component unisim_iddr_reg is
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generic ( tech : integer := virtex4);
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port(
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Q1 : out std_ulogic;
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Q2 : out std_ulogic;
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C1 : in std_ulogic;
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C2 : in std_ulogic;
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CE : in std_ulogic;
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D : in std_ulogic;
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R : in std_ulogic;
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S : in std_ulogic
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);
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end component;
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component gen_iddr_reg
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port (
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Q1 : out std_ulogic;
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Q2 : out std_ulogic;
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C1 : in std_ulogic;
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C2 : in std_ulogic;
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CE : in std_ulogic;
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D : in std_ulogic;
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R : in std_ulogic;
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S : in std_ulogic);
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end component;
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component ec_oddr_reg
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port (
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Q : out std_ulogic;
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C1 : in std_ulogic;
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C2 : in std_ulogic;
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CE : in std_ulogic;
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D1 : in std_ulogic;
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D2 : in std_ulogic;
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R : in std_ulogic;
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S : in std_ulogic);
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end component;
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component unisim_oddr_reg
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generic ( tech : integer := virtex4);
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port (
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Q : out std_ulogic;
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C1 : in std_ulogic;
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C2 : in std_ulogic;
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CE : in std_ulogic;
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D1 : in std_ulogic;
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D2 : in std_ulogic;
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R : in std_ulogic;
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S : in std_ulogic);
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end component;
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component gen_oddr_reg
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port (
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Q : out std_ulogic;
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C1 : in std_ulogic;
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C2 : in std_ulogic;
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CE : in std_ulogic;
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D1 : in std_ulogic;
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D2 : in std_ulogic;
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R : in std_ulogic;
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S : in std_ulogic);
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end component;
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component spartan3e_ddr_phy
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generic (MHz : integer := 100; rstdelay : integer := 200;
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dbits : integer := 16; clk_mul : integer := 2 ;
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clk_div : integer := 2; rskew : integer := 0);
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port (
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rst : in std_ulogic;
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clk : in std_logic; -- input clock
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clkout : out std_ulogic; -- DDR state clock
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clkread : out std_ulogic; -- DDR read clock
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lock : out std_ulogic; -- DCM locked
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ddr_clk : out std_logic_vector(2 downto 0);
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ddr_clkb : out std_logic_vector(2 downto 0);
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ddr_clk_fb_out : out std_logic;
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ddr_clk_fb : in std_logic;
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ddr_cke : out std_logic_vector(1 downto 0);
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ddr_csb : out std_logic_vector(1 downto 0);
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ddr_web : out std_ulogic; -- ddr write enable
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ddr_rasb : out std_ulogic; -- ddr ras
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ddr_casb : out std_ulogic; -- ddr cas
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ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
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ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
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ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
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ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
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ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
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addr : in std_logic_vector (13 downto 0); -- data mask
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ba : in std_logic_vector ( 1 downto 0); -- data mask
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dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
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dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
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dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
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oen : in std_ulogic;
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dqs : in std_ulogic;
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dqsoen : in std_ulogic;
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rasn : in std_ulogic;
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casn : in std_ulogic;
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wen : in std_ulogic;
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csn : in std_logic_vector(1 downto 0);
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cke : in std_logic_vector(1 downto 0)
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);
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end component;
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component virtex4_ddr_phy
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generic (MHz : integer := 100; rstdelay : integer := 200;
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dbits : integer := 16; clk_mul : integer := 2 ;
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clk_div : integer := 2; rskew : integer := 0);
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port (
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rst : in std_ulogic;
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clk : in std_logic; -- input clock
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clkout : out std_ulogic; -- system clock
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lock : out std_ulogic; -- DCM locked
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ddr_clk : out std_logic_vector(2 downto 0);
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ddr_clkb : out std_logic_vector(2 downto 0);
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ddr_clk_fb_out : out std_logic;
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ddr_clk_fb : in std_logic;
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ddr_cke : out std_logic_vector(1 downto 0);
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ddr_csb : out std_logic_vector(1 downto 0);
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ddr_web : out std_ulogic; -- ddr write enable
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ddr_rasb : out std_ulogic; -- ddr ras
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ddr_casb : out std_ulogic; -- ddr cas
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ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
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ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
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ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
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ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
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ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
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addr : in std_logic_vector (13 downto 0); -- data mask
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ba : in std_logic_vector ( 1 downto 0); -- data mask
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dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
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dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
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dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
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oen : in std_ulogic;
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dqs : in std_ulogic;
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dqsoen : in std_ulogic;
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rasn : in std_ulogic;
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casn : in std_ulogic;
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wen : in std_ulogic;
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csn : in std_logic_vector(1 downto 0);
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cke : in std_logic_vector(1 downto 0);
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ck : in std_logic_vector(2 downto 0)
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);
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end component;
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component virtex2_ddr_phy
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generic (MHz : integer := 100; rstdelay : integer := 200;
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dbits : integer := 16; clk_mul : integer := 2 ;
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clk_div : integer := 2; rskew : integer := 0);
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port (
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rst : in std_ulogic;
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clk : in std_logic; -- input clock
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clkout : out std_ulogic; -- system clock
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lock : out std_ulogic; -- DCM locked
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ddr_clk : out std_logic_vector(2 downto 0);
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ddr_clkb : out std_logic_vector(2 downto 0);
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ddr_clk_fb_out : out std_logic;
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ddr_clk_fb : in std_logic;
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ddr_cke : out std_logic_vector(1 downto 0);
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ddr_csb : out std_logic_vector(1 downto 0);
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ddr_web : out std_ulogic; -- ddr write enable
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ddr_rasb : out std_ulogic; -- ddr ras
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ddr_casb : out std_ulogic; -- ddr cas
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ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
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ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
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ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
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ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
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ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
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addr : in std_logic_vector (13 downto 0); -- data mask
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ba : in std_logic_vector ( 1 downto 0); -- data mask
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dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
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dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
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dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
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oen : in std_ulogic;
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dqs : in std_ulogic;
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dqsoen : in std_ulogic;
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rasn : in std_ulogic;
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casn : in std_ulogic;
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wen : in std_ulogic;
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csn : in std_logic_vector(1 downto 0);
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cke : in std_logic_vector(1 downto 0)
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);
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end component;
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component stratixii_ddr_phy
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generic (MHz : integer := 100; rstdelay : integer := 200;
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dbits : integer := 16; clk_mul : integer := 2 ;
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clk_div : integer := 2);
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port (
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rst : in std_ulogic;
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clk : in std_logic; -- input clock
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clkout : out std_ulogic; -- system clock
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lock : out std_ulogic; -- DCM locked
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ddr_clk : out std_logic_vector(2 downto 0);
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ddr_clkb : out std_logic_vector(2 downto 0);
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ddr_clk_fb_out : out std_logic;
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ddr_clk_fb : in std_logic;
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ddr_cke : out std_logic_vector(1 downto 0);
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ddr_csb : out std_logic_vector(1 downto 0);
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ddr_web : out std_ulogic; -- ddr write enable
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ddr_rasb : out std_ulogic; -- ddr ras
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ddr_casb : out std_ulogic; -- ddr cas
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ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
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ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
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ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
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ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
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ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
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addr : in std_logic_vector (13 downto 0); -- data mask
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ba : in std_logic_vector ( 1 downto 0); -- data mask
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dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
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dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
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dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
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oen : in std_ulogic;
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dqs : in std_ulogic;
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dqsoen : in std_ulogic;
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rasn : in std_ulogic;
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casn : in std_ulogic;
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wen : in std_ulogic;
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csn : in std_logic_vector(1 downto 0);
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cke : in std_logic_vector(1 downto 0)
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);
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end component;
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component cycloneiii_ddr_phy
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generic (MHz : integer := 100; rstdelay : integer := 200;
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dbits : integer := 16; clk_mul : integer := 2 ;
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clk_div : integer := 2; rskew : integer := 0);
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port (
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rst : in std_ulogic;
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clk : in std_logic; -- input clock
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clkout : out std_ulogic; -- system clock
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lock : out std_ulogic; -- DCM locked
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ddr_clk : out std_logic_vector(2 downto 0);
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ddr_clkb : out std_logic_vector(2 downto 0);
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ddr_clk_fb_out : out std_logic;
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ddr_clk_fb : in std_logic;
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ddr_cke : out std_logic_vector(1 downto 0);
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285 |
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ddr_csb : out std_logic_vector(1 downto 0);
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286 |
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ddr_web : out std_ulogic; -- ddr write enable
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287 |
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ddr_rasb : out std_ulogic; -- ddr ras
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288 |
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ddr_casb : out std_ulogic; -- ddr cas
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ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
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ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
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ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
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ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
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293 |
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ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
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294 |
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295 |
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addr : in std_logic_vector (13 downto 0); -- data mask
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296 |
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ba : in std_logic_vector ( 1 downto 0); -- data mask
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297 |
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dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
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298 |
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dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
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299 |
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dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
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300 |
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oen : in std_ulogic;
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301 |
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dqs : in std_ulogic;
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dqsoen : in std_ulogic;
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303 |
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rasn : in std_ulogic;
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304 |
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casn : in std_ulogic;
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305 |
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wen : in std_ulogic;
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306 |
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csn : in std_logic_vector(1 downto 0);
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307 |
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cke : in std_logic_vector(1 downto 0)
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);
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309 |
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310 |
|
|
end component;
|
311 |
|
|
|
312 |
|
|
component generic_ddr_phy
|
313 |
|
|
generic (MHz : integer := 100; rstdelay : integer := 200;
|
314 |
|
|
dbits : integer := 16; clk_mul : integer := 2 ;
|
315 |
|
|
clk_div : integer := 2; rskew : integer := 0; mobile : integer := 0);
|
316 |
|
|
|
317 |
|
|
port (
|
318 |
|
|
rst : in std_ulogic;
|
319 |
|
|
clk : in std_logic; -- input clock
|
320 |
|
|
clkout : out std_ulogic; -- system clock
|
321 |
|
|
lock : out std_ulogic; -- DCM locked
|
322 |
|
|
|
323 |
|
|
ddr_clk : out std_logic_vector(2 downto 0);
|
324 |
|
|
ddr_clkb : out std_logic_vector(2 downto 0);
|
325 |
|
|
ddr_clk_fb_out : out std_logic;
|
326 |
|
|
ddr_clk_fb : in std_logic;
|
327 |
|
|
ddr_cke : out std_logic_vector(1 downto 0);
|
328 |
|
|
ddr_csb : out std_logic_vector(1 downto 0);
|
329 |
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
330 |
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
331 |
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
332 |
|
|
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
|
333 |
|
|
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0);-- ddr dqs
|
334 |
|
|
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
|
335 |
|
|
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
|
336 |
|
|
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
|
337 |
|
|
|
338 |
|
|
addr : in std_logic_vector (13 downto 0); -- data mask
|
339 |
|
|
ba : in std_logic_vector ( 1 downto 0); -- data mask
|
340 |
|
|
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
341 |
|
|
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
342 |
|
|
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
|
343 |
|
|
oen : in std_ulogic;
|
344 |
|
|
dqs : in std_ulogic;
|
345 |
|
|
dqsoen : in std_ulogic;
|
346 |
|
|
rasn : in std_ulogic;
|
347 |
|
|
casn : in std_ulogic;
|
348 |
|
|
wen : in std_ulogic;
|
349 |
|
|
csn : in std_logic_vector(1 downto 0);
|
350 |
|
|
cke : in std_logic_vector(1 downto 0);
|
351 |
|
|
ck : in std_logic_vector(2 downto 0);
|
352 |
|
|
moben : in std_logic
|
353 |
|
|
);
|
354 |
|
|
|
355 |
|
|
end component;
|
356 |
|
|
|
357 |
|
|
component tsmc90_tci_ddr_phy
|
358 |
|
|
generic (MHz : integer := 100; rstdelay : integer := 200;
|
359 |
|
|
dbits : integer := 16);
|
360 |
|
|
|
361 |
|
|
port (
|
362 |
|
|
rst : in std_ulogic;
|
363 |
|
|
clk : in std_logic; -- input clock
|
364 |
|
|
clk90_sigi_0 : in std_logic;
|
365 |
|
|
rclk_sigi_1 : in std_logic;
|
366 |
|
|
clkout : out std_ulogic; -- system clock
|
367 |
|
|
lock : out std_ulogic; -- DCM locked
|
368 |
|
|
|
369 |
|
|
ddr_clk : out std_logic_vector(2 downto 0);
|
370 |
|
|
ddr_clkb : out std_logic_vector(2 downto 0);
|
371 |
|
|
--ddr_clk_fb_out : out std_logic;
|
372 |
|
|
--ddr_clk_fb : in std_logic;
|
373 |
|
|
ddr_cke : out std_logic_vector(1 downto 0);
|
374 |
|
|
ddr_csb : out std_logic_vector(1 downto 0);
|
375 |
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
376 |
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
377 |
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
378 |
|
|
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
|
379 |
|
|
ddr_dqsin : in std_logic_vector (dbits/8-1 downto 0);-- ddr dqs
|
380 |
|
|
ddr_dqsout : out std_logic_vector (dbits/8-1 downto 0);-- ddr dqs
|
381 |
|
|
ddr_dqsoen : out std_logic_vector (dbits/8-1 downto 0);-- ddr dqs
|
382 |
|
|
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
|
383 |
|
|
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
|
384 |
|
|
ddr_dqin : in std_logic_vector (dbits-1 downto 0); -- ddr data
|
385 |
|
|
ddr_dqout : out std_logic_vector (dbits-1 downto 0); -- ddr data
|
386 |
|
|
ddr_dqoen : out std_logic_vector (dbits-1 downto 0); -- ddr data
|
387 |
|
|
|
388 |
|
|
addr : in std_logic_vector (13 downto 0); -- data mask
|
389 |
|
|
ba : in std_logic_vector ( 1 downto 0); -- data mask
|
390 |
|
|
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
391 |
|
|
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
392 |
|
|
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
|
393 |
|
|
oen : in std_ulogic;
|
394 |
|
|
dqs : in std_ulogic;
|
395 |
|
|
dqsoen : in std_ulogic;
|
396 |
|
|
rasn : in std_ulogic;
|
397 |
|
|
casn : in std_ulogic;
|
398 |
|
|
wen : in std_ulogic;
|
399 |
|
|
csn : in std_logic_vector(1 downto 0);
|
400 |
|
|
cke : in std_logic_vector(1 downto 0);
|
401 |
|
|
ck : in std_logic_vector(2 downto 0);
|
402 |
|
|
moben : in std_logic;
|
403 |
|
|
conf : in std_logic_vector(63 downto 0);
|
404 |
|
|
tstclkout : out std_logic_vector(3 downto 0)
|
405 |
|
|
);
|
406 |
|
|
|
407 |
|
|
end component;
|
408 |
|
|
|
409 |
|
|
component virtex5_ddr2_phy
|
410 |
|
|
generic (MHz : integer := 100; rstdelay : integer := 200;
|
411 |
|
|
dbits : integer := 16; clk_mul : integer := 2 ; clk_div : integer := 2;
|
412 |
|
|
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
|
413 |
|
|
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
|
414 |
|
|
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
|
415 |
|
|
numidelctrl : integer := 4; norefclk : integer := 0;
|
416 |
|
|
tech : integer := virtex5);
|
417 |
|
|
|
418 |
|
|
port (
|
419 |
|
|
rst : in std_ulogic;
|
420 |
|
|
clk : in std_logic; -- input clock
|
421 |
|
|
clkref200 : in std_logic; -- input 200MHz clock
|
422 |
|
|
clkout : out std_ulogic; -- system clock
|
423 |
|
|
lock : out std_ulogic; -- DCM locked
|
424 |
|
|
|
425 |
|
|
ddr_clk : out std_logic_vector(2 downto 0);
|
426 |
|
|
ddr_clkb : out std_logic_vector(2 downto 0);
|
427 |
|
|
ddr_cke : out std_logic_vector(1 downto 0);
|
428 |
|
|
ddr_csb : out std_logic_vector(1 downto 0);
|
429 |
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
430 |
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
431 |
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
432 |
|
|
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
|
433 |
|
|
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
|
434 |
|
|
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
|
435 |
|
|
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
|
436 |
|
|
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
|
437 |
|
|
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
|
438 |
|
|
ddr_odt : out std_logic_vector(1 downto 0);
|
439 |
|
|
|
440 |
|
|
addr : in std_logic_vector (13 downto 0); -- data mask
|
441 |
|
|
ba : in std_logic_vector ( 1 downto 0); -- data mask
|
442 |
|
|
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
443 |
|
|
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
444 |
|
|
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
|
445 |
|
|
oen : in std_ulogic;
|
446 |
|
|
dqs : in std_ulogic;
|
447 |
|
|
dqsoen : in std_ulogic;
|
448 |
|
|
rasn : in std_ulogic;
|
449 |
|
|
casn : in std_ulogic;
|
450 |
|
|
wen : in std_ulogic;
|
451 |
|
|
csn : in std_logic_vector(1 downto 0);
|
452 |
|
|
cke : in std_logic_vector(1 downto 0);
|
453 |
|
|
cal_en : in std_logic_vector(dbits/8-1 downto 0);
|
454 |
|
|
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
|
455 |
|
|
cal_rst : in std_logic;
|
456 |
|
|
odt : in std_logic_vector(1 downto 0)
|
457 |
|
|
);
|
458 |
|
|
end component;
|
459 |
|
|
|
460 |
|
|
component stratixiii_ddr2_phy
|
461 |
|
|
generic (MHz : integer := 100; rstdelay : integer := 200;
|
462 |
|
|
dbits : integer := 16; clk_mul : integer := 2 ; clk_div : integer := 2;
|
463 |
|
|
ddelayb0 : integer := 0; ddelayb1 : integer := 0; ddelayb2 : integer := 0;
|
464 |
|
|
ddelayb3 : integer := 0; ddelayb4 : integer := 0; ddelayb5 : integer := 0;
|
465 |
|
|
ddelayb6 : integer := 0; ddelayb7 : integer := 0;
|
466 |
|
|
numidelctrl : integer := 4; norefclk : integer := 0;
|
467 |
|
|
tech : integer := stratix3; rskew : integer := 0);
|
468 |
|
|
|
469 |
|
|
port (
|
470 |
|
|
rst : in std_ulogic;
|
471 |
|
|
clk : in std_logic; -- input clock
|
472 |
|
|
clkref200 : in std_logic; -- input 200MHz clock
|
473 |
|
|
clkout : out std_ulogic; -- system clock
|
474 |
|
|
lock : out std_ulogic; -- DCM locked
|
475 |
|
|
|
476 |
|
|
ddr_clk : out std_logic_vector(2 downto 0);
|
477 |
|
|
ddr_clkb : out std_logic_vector(2 downto 0);
|
478 |
|
|
ddr_cke : out std_logic_vector(1 downto 0);
|
479 |
|
|
ddr_csb : out std_logic_vector(1 downto 0);
|
480 |
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
481 |
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
482 |
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
483 |
|
|
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
|
484 |
|
|
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
|
485 |
|
|
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
|
486 |
|
|
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
|
487 |
|
|
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
|
488 |
|
|
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
|
489 |
|
|
ddr_odt : out std_logic_vector(1 downto 0);
|
490 |
|
|
|
491 |
|
|
addr : in std_logic_vector (13 downto 0); -- data mask
|
492 |
|
|
ba : in std_logic_vector ( 1 downto 0); -- data mask
|
493 |
|
|
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
494 |
|
|
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr input data
|
495 |
|
|
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
|
496 |
|
|
oen : in std_ulogic;
|
497 |
|
|
dqs : in std_ulogic;
|
498 |
|
|
dqsoen : in std_ulogic;
|
499 |
|
|
rasn : in std_ulogic;
|
500 |
|
|
casn : in std_ulogic;
|
501 |
|
|
wen : in std_ulogic;
|
502 |
|
|
csn : in std_logic_vector(1 downto 0);
|
503 |
|
|
cke : in std_logic_vector(1 downto 0);
|
504 |
|
|
cal_en : in std_logic_vector(dbits/8-1 downto 0);
|
505 |
|
|
cal_inc : in std_logic_vector(dbits/8-1 downto 0);
|
506 |
|
|
cal_pll : in std_logic_vector(1 downto 0);
|
507 |
|
|
cal_rst : in std_logic;
|
508 |
|
|
odt : in std_logic_vector(1 downto 0)
|
509 |
|
|
);
|
510 |
|
|
end component;
|
511 |
|
|
|
512 |
|
|
|
513 |
|
|
component spartan3a_ddr2_phy
|
514 |
|
|
generic (MHz : integer := 125; rstdelay : integer := 200;
|
515 |
|
|
dbits : integer := 16; clk_mul : integer := 2;
|
516 |
|
|
clk_div : integer := 2; tech : integer := spartan3;
|
517 |
|
|
rskew : integer := 0);
|
518 |
|
|
port (
|
519 |
|
|
rst : in std_ulogic;
|
520 |
|
|
clk : in std_logic; -- input clock
|
521 |
|
|
clkout : out std_ulogic; -- system clock
|
522 |
|
|
lock : out std_ulogic; -- DCM locked
|
523 |
|
|
|
524 |
|
|
ddr_clk : out std_logic_vector(2 downto 0);
|
525 |
|
|
ddr_clkb : out std_logic_vector(2 downto 0);
|
526 |
|
|
ddr_clk_fb_out : out std_logic;
|
527 |
|
|
ddr_clk_fb : in std_logic;
|
528 |
|
|
ddr_cke : out std_logic_vector(1 downto 0);
|
529 |
|
|
ddr_csb : out std_logic_vector(1 downto 0);
|
530 |
|
|
ddr_web : out std_ulogic; -- ddr write enable
|
531 |
|
|
ddr_rasb : out std_ulogic; -- ddr ras
|
532 |
|
|
ddr_casb : out std_ulogic; -- ddr cas
|
533 |
|
|
ddr_dm : out std_logic_vector (dbits/8-1 downto 0); -- ddr dm
|
534 |
|
|
ddr_dqs : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqs
|
535 |
|
|
ddr_dqsn : inout std_logic_vector (dbits/8-1 downto 0); -- ddr dqsn
|
536 |
|
|
ddr_ad : out std_logic_vector (13 downto 0); -- ddr address
|
537 |
|
|
ddr_ba : out std_logic_vector (1 downto 0); -- ddr bank address
|
538 |
|
|
ddr_dq : inout std_logic_vector (dbits-1 downto 0); -- ddr data
|
539 |
|
|
ddr_odt : out std_logic_vector(1 downto 0);
|
540 |
|
|
|
541 |
|
|
addr : in std_logic_vector (13 downto 0);
|
542 |
|
|
ba : in std_logic_vector ( 1 downto 0);
|
543 |
|
|
dqin : out std_logic_vector (dbits*2-1 downto 0); -- ddr data
|
544 |
|
|
dqout : in std_logic_vector (dbits*2-1 downto 0); -- ddr data
|
545 |
|
|
dm : in std_logic_vector (dbits/4-1 downto 0); -- data mask
|
546 |
|
|
oen : in std_ulogic;
|
547 |
|
|
dqs : in std_ulogic;
|
548 |
|
|
dqsoen : in std_ulogic;
|
549 |
|
|
rasn : in std_ulogic;
|
550 |
|
|
casn : in std_ulogic;
|
551 |
|
|
wen : in std_ulogic;
|
552 |
|
|
csn : in std_logic_vector(1 downto 0);
|
553 |
|
|
cke : in std_logic_vector(1 downto 0);
|
554 |
|
|
cal_pll : in std_logic_vector(1 downto 0);
|
555 |
|
|
odt : in std_logic_vector(1 downto 0)
|
556 |
|
|
);
|
557 |
|
|
end component;
|
558 |
|
|
end;
|