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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: inpad
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-- File: inpad.vhd
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-- Author: Jiri Gaisler - Gaisler Research
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-- Description: input pad with technology wrapper
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------------------------------------------------------------------------------
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library techmap;
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library ieee;
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use ieee.std_logic_1164.all;
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use techmap.gencomp.all;
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use techmap.allpads.all;
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entity inpad is
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generic (tech : integer := 0; level : integer := 0;
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voltage : integer := x33v; filter : integer := 0;
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strength : integer := 0);
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port (pad : in std_ulogic; o : out std_ulogic);
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end;
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architecture rtl of inpad is
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begin
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gen0 : if has_pads(tech) = 0 generate
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o <= to_X01(pad) after 1 ns;
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end generate;
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xcv : if (tech = virtex) or (tech = virtex2) or (tech = spartan3) or
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(tech = virtex4) or (tech = spartan3e) or (tech = virtex5)
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generate
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x0 : virtex_inpad generic map (level, voltage) port map (pad, o);
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end generate;
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axc : if (tech = axcel) or (tech = proasic) or (tech = apa3) generate
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x0 : axcel_inpad generic map (level, voltage) port map (pad, o);
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end generate;
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atc : if (tech = atc18s) generate
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x0 : atc18_inpad generic map (level, voltage) port map (pad, o);
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end generate;
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atcrh : if (tech = atc18rha) generate
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x0 : atc18rha_inpad generic map (level, voltage) port map (pad, o);
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end generate;
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um : if (tech = umc) generate
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x0 : umc_inpad generic map (level, voltage, filter) port map (pad, o);
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end generate;
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rhu : if (tech = rhumc) generate
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x0 : rhumc_inpad generic map (level, voltage, filter) port map (pad, o);
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end generate;
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ihp : if (tech = ihp25) generate
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x0 : ihp25_inpad generic map(level, voltage) port map(pad, o);
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end generate;
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ihprh : if (tech = ihp25rh) generate
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x0 : ihp25rh_inpad generic map(level, voltage) port map(pad, o);
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end generate;
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rh18t : if (tech = rhlib18t) generate
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x0 : rh_lib18t_inpad generic map (voltage, filter) port map(pad, o);
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end generate;
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ut025 : if (tech = ut25) generate
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x0 : ut025crh_inpad generic map (level, voltage, filter) port map(pad, o);
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end generate;
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pereg : if (tech = peregrine) generate
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x0 : peregrine_inpad generic map (level, voltage, filter, strength) port map(pad, o);
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end generate;
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eas : if (tech = easic90) generate
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x0 : nextreme_inpad generic map (level, voltage) port map (pad, o);
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end generate;
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end;
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library techmap;
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library ieee;
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use ieee.std_logic_1164.all;
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use techmap.gencomp.all;
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entity inpadv is
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generic (tech : integer := 0; level : integer := 0;
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voltage : integer := 0; width : integer := 1);
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port (
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pad : in std_logic_vector(width-1 downto 0);
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o : out std_logic_vector(width-1 downto 0));
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end;
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architecture rtl of inpadv is
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begin
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v : for i in width-1 downto 0 generate
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x0 : inpad generic map (tech, level, voltage) port map (pad(i), o(i));
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end generate;
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end;
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