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dimamali |
------------------------------------------------------------------------------
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-- This file is a part of the GRLIB VHDL IP LIBRARY
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-- Copyright (C) 2003, Gaisler Research
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2 of the License, or
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-- (at your option) any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; if not, write to the Free Software
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-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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-----------------------------------------------------------------------------
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-- Entity: various
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-- File: mem_umc_gen.vhd
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-- Author: Jiri Gaisler Gaisler Research
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-- Description: Memory generators for UMC rams
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------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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-- pragma translate_off
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library umc18;
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use umc18.SRAM_2048wx32b;
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use umc18.SRAM_1024wx32b;
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use umc18.SRAM_512wx32b;
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use umc18.SRAM_256wx32b;
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use umc18.SRAM_128wx32b;
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use umc18.SRAM_64wx32b;
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use umc18.SRAM_32wx32b;
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use umc18.SRAM_2048wx40b;
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use umc18.SRAM_1024wx40b;
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use umc18.SRAM_512wx40b;
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use umc18.SRAM_256wx40b;
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use umc18.SRAM_128wx40b;
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use umc18.SRAM_64wx40b;
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use umc18.SRAM_32wx40b;
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-- pragma translate_on
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entity umc_syncram is
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generic ( abits : integer := 10; dbits : integer := 8 );
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port (
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clk : in std_ulogic;
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address : in std_logic_vector(abits -1 downto 0);
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datain : in std_logic_vector(dbits -1 downto 0);
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dataout : out std_logic_vector(dbits -1 downto 0);
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enable : in std_ulogic;
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write : in std_ulogic
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);
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end;
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architecture rtl of umc_syncram is
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component SRAM_2048wx32b is
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port (
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a : in std_logic_vector(10 downto 0);
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data : in std_logic_vector(31 downto 0);
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csn : in std_logic;
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wen : in std_logic;
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oen : in std_logic;
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q : out std_logic_vector(31 downto 0);
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clk : in std_logic
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);
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end component;
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component SRAM_1024wx32b is
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port (
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a : in std_logic_vector(9 downto 0);
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data : in std_logic_vector(31 downto 0);
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csn : in std_logic;
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wen : in std_logic;
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oen : in std_logic;
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q : out std_logic_vector(31 downto 0);
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clk : in std_logic
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);
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end component;
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component SRAM_512wx32b is
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port (
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a : in std_logic_vector(8 downto 0);
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data : in std_logic_vector(31 downto 0);
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csn : in std_logic;
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wen : in std_logic;
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oen : in std_logic;
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q : out std_logic_vector(31 downto 0);
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clk : in std_logic
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);
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end component;
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component SRAM_256wx32b is
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port (
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a : in std_logic_vector(7 downto 0);
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data : in std_logic_vector(31 downto 0);
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csn : in std_logic;
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wen : in std_logic;
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oen : in std_logic;
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q : out std_logic_vector(31 downto 0);
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clk : in std_logic
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);
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end component;
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component SRAM_128wx32b is
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port (
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a : in std_logic_vector(6 downto 0);
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data : in std_logic_vector(31 downto 0);
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csn : in std_logic;
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wen : in std_logic;
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oen : in std_logic;
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q : out std_logic_vector(31 downto 0);
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clk : in std_logic
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);
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end component;
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component SRAM_64wx32b is
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port (
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a : in std_logic_vector(5 downto 0);
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data : in std_logic_vector(31 downto 0);
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csn : in std_logic;
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wen : in std_logic;
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oen : in std_logic;
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q : out std_logic_vector(31 downto 0);
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clk : in std_logic
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);
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end component;
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component SRAM_32wx32b is
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port (
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a : in std_logic_vector(4 downto 0);
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data : in std_logic_vector(31 downto 0);
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csn : in std_logic;
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wen : in std_logic;
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oen : in std_logic;
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q : out std_logic_vector(31 downto 0);
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clk : in std_logic
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);
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end component;
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component SRAM_2048wx40b is
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port (
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a : in std_logic_vector(10 downto 0);
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data : in std_logic_vector(39 downto 0);
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csn : in std_logic;
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wen : in std_logic;
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oen : in std_logic;
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q : out std_logic_vector(39 downto 0);
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clk : in std_logic
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);
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end component;
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component SRAM_1024wx40b is
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port (
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a : in std_logic_vector(9 downto 0);
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data : in std_logic_vector(39 downto 0);
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csn : in std_logic;
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wen : in std_logic;
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oen : in std_logic;
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q : out std_logic_vector(39 downto 0);
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clk : in std_logic
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);
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end component;
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component SRAM_512wx40b is
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port (
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a : in std_logic_vector(8 downto 0);
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data : in std_logic_vector(39 downto 0);
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csn : in std_logic;
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wen : in std_logic;
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oen : in std_logic;
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q : out std_logic_vector(39 downto 0);
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clk : in std_logic
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);
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end component;
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component SRAM_256wx40b is
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port (
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a : in std_logic_vector(7 downto 0);
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data : in std_logic_vector(39 downto 0);
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csn : in std_logic;
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wen : in std_logic;
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oen : in std_logic;
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q : out std_logic_vector(39 downto 0);
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clk : in std_logic
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);
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end component;
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component SRAM_128wx40b is
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port (
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a : in std_logic_vector(6 downto 0);
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data : in std_logic_vector(39 downto 0);
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csn : in std_logic;
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wen : in std_logic;
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oen : in std_logic;
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q : out std_logic_vector(39 downto 0);
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clk : in std_logic
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);
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end component;
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component SRAM_64wx40b is
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port (
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a : in std_logic_vector(5 downto 0);
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data : in std_logic_vector(39 downto 0);
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csn : in std_logic;
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wen : in std_logic;
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oen : in std_logic;
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q : out std_logic_vector(39 downto 0);
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clk : in std_logic
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);
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end component;
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component SRAM_32wx40b is
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port (
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a : in std_logic_vector(4 downto 0);
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data : in std_logic_vector(39 downto 0);
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csn : in std_logic;
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wen : in std_logic;
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oen : in std_logic;
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q : out std_logic_vector(39 downto 0);
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clk : in std_logic
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);
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end component;
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signal d, q, gnd : std_logic_vector(41 downto 0);
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signal a : std_logic_vector(17 downto 0);
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signal vcc, csn, wen : std_ulogic;
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constant synopsys_bug : std_logic_vector(41 downto 0) := (others => '0');
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begin
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csn <= not enable; wen <= not write;
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gnd <= (others => '0'); vcc <= '1';
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a(abits -1 downto 0) <= address;
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d(dbits -1 downto 0) <= datain(dbits -1 downto 0);
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a(17 downto abits) <= synopsys_bug(17 downto abits);
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d(41 downto dbits) <= synopsys_bug(41 downto dbits);
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dataout <= q(dbits -1 downto 0);
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-- q(41 downto dbits) <= synopsys_bug(41 downto dbits);
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d32 : if (dbits <= 32) generate
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a5d32 : if (abits <= 5) generate
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id0 : SRAM_32wx32b port map (a(4 downto 0), d(31 downto 0), csn,
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wen, gnd(0), q(31 downto 0), clk);
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end generate;
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a6d32 : if (abits = 6) generate
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id0 : SRAM_64wx32b port map (a(5 downto 0), d(31 downto 0), csn,
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wen, gnd(0), q(31 downto 0), clk);
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end generate;
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a7d32 : if (abits = 7) generate
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id0 : SRAM_128wx32b port map (a(6 downto 0), d(31 downto 0), csn,
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wen, gnd(0), q(31 downto 0), clk);
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end generate;
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a8d32 : if (abits = 8) generate
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id0 : SRAM_256wx32b port map (a(7 downto 0), d(31 downto 0), csn,
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wen, gnd(0), q(31 downto 0), clk);
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end generate;
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a9d32 : if (abits = 9) generate
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id0 : SRAM_512wx32b port map (a(8 downto 0), d(31 downto 0), csn,
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wen, gnd(0), q(31 downto 0), clk);
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end generate;
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a10d32 : if (abits = 10) generate
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id0 : SRAM_1024wx32b port map (a(9 downto 0), d(31 downto 0), csn,
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wen, gnd(0), q(31 downto 0), clk);
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end generate;
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a11d32 : if (abits = 11) generate
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id0 : SRAM_2048wx32b port map (a(10 downto 0), d(31 downto 0), csn,
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wen, gnd(0), q(31 downto 0), clk);
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end generate;
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end generate;
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d40 : if (dbits > 32) and (dbits <= 40) generate
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a5d40 : if (abits <= 5) generate
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id0 : SRAM_32wx40b port map (a(4 downto 0), d(39 downto 0), csn,
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wen, gnd(0), q(39 downto 0), clk);
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end generate;
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a6d40 : if (abits = 6) generate
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id0 : SRAM_64wx40b port map (a(5 downto 0), d(39 downto 0), csn,
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wen, gnd(0), q(39 downto 0), clk);
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end generate;
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a7d40 : if (abits = 7) generate
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id0 : SRAM_128wx40b port map (a(6 downto 0), d(39 downto 0), csn,
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wen, gnd(0), q(39 downto 0), clk);
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end generate;
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a8d40 : if (abits = 8) generate
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id0 : SRAM_256wx40b port map (a(7 downto 0), d(39 downto 0), csn,
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wen, gnd(0), q(39 downto 0), clk);
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end generate;
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a9d40 : if (abits = 9) generate
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id0 : SRAM_512wx40b port map (a(8 downto 0), d(39 downto 0), csn,
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wen, gnd(0), q(39 downto 0), clk);
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end generate;
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a10d40 : if (abits = 10) generate
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id0 : SRAM_1024wx40b port map (a(9 downto 0), d(39 downto 0), csn,
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wen, gnd(0), q(39 downto 0), clk);
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end generate;
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a11d40 : if (abits = 11) generate
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id0 : SRAM_2048wx40b port map (a(10 downto 0), d(39 downto 0), csn,
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wen, gnd(0), q(39 downto 0), clk);
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end generate;
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end generate;
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-- pragma translate_off
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a_to_high : if (abits > 12) or (dbits > 40) generate
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x : process
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begin
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assert false
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report "Unsupported memory size (umc18)"
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severity failure;
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wait;
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end process;
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end generate;
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-- pragma translate_on
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end;
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