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[/] [mipsr2000/] [trunk/] [RAMB16_S9_0.vhd] - Blame information for rev 37

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1 37 jimi39 
----------------------------------------------------------------------------------
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-- Company:
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-- Engineer:    Lazaridis Dimitris
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--
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-- Create Date:    22:46:06 06/13/2012
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-- Design Name:
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-- Module Name:    RAMB16_S9_0 - Behavioral
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-- Project Name:
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-- Target Devices:
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-- Tool versions:
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-- Description:
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--
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-- Dependencies:
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--
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-- Revision:
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-- Revision 0.01 - File Created
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-- Additional Comments:
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--
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----------------------------------------------------------------------------------
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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use IEEE.STD_LOGIC_ARITH.ALL;
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--use IEEE.STD_LOGIC_UNSIGNED.ALL;
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Library UNISIM;
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use UNISIM.vcomponents.all;
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-- Uncomment the following library declaration if using
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-- arithmetic functions with Signed or Unsigned values
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--use IEEE.NUMERIC_STD.ALL;
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-- Uncomment the following library declaration if instantiating
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-- any Xilinx primitives in this code.
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--library UNISIM;
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--use UNISIM.VComponents.all;
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entity RAMB16_S9_0 is
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port (
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       clk : in std_logic;
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       we : in std_logic;
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       en : in std_logic;
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       ssr : in std_logic;
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       addr : in std_logic_vector(10 downto 0);
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       di : in std_logic_vector (7 downto 0);
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       do : out std_logic_vector(7 downto 0)
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                );
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end RAMB16_S9_0;
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architecture Behavioral of RAMB16_S9_0 is
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signal clk_inv : std_logic;
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begin
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     process(clk)
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          variable invert : std_logic;
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          begin
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          invert := not clk;
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          clk_inv <= invert;
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          end process;
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     RAMB16_S9_inst : RAMB16_S9
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   generic map (
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      INIT => X"000", --  Value of output RAM registers at startup
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      SRVAL => X"000", --  Ouput value upon SSR assertion
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      WRITE_MODE => "WRITE_FIRST", --  WRITE_FIRST, READ_FIRST or NO_CHANGE
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      -- The following INIT_xx declarations specify the initial contents of the RAM
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      -- Address 0 to 511
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      INIT_00 => X"DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD0DDDDDDDDDDDDDDDDD",
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      INIT_01 => X"DD0000D0DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD",
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      INIT_02 => X"DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD",
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      INIT_03 => X"DFDDDDDFDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDFDDDDDF",
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      INIT_04 => X"DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD",
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      INIT_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_07 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_08 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_09 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_0A => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_0B => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_0C => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_0D => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_0E => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_0F => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
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      -- Address 512 to 1023
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      INIT_10 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
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      INIT_11 => X"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF",
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      INIT_12 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_13 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_14 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_15 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_16 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_17 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_18 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_19 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_1A => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_1B => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_1C => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_1D => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_1E => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_1F => X"0000000000000000000000000000000000000000000000000000000000000000",
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      -- Address 1024 to 1535
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      INIT_20 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_21 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_22 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_23 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_24 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_25 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_26 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_27 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_28 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_29 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_2A => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_2B => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_2C => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_2D => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_2E => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_2F => X"0000000000000000000000000000000000000000000000000000000000000000",
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      -- Address 1536 to 2047
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      INIT_30 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_31 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_32 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_33 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_34 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_35 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_36 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_37 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_38 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_39 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_3A => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_3B => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_3C => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_3D => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_3E => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INIT_3F => X"0000000000000000000000000000000000000000000000000000000000000000",
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      -- The next set of INITP_xx are for the parity bits
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      -- Address 0 to 511
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      INITP_00 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INITP_01 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      -- Address 512 to 1023
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      INITP_02 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INITP_03 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      -- Address 1024 to 1535
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      INITP_04 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INITP_05 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      -- Address 1536 to 2047
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      INITP_06 => X"0000000000000000000000000000000000000000000000000000000000000000",
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      INITP_07 => X"0000000000000000000000000000000000000000000000000000000000000000")
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   port map (
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      DO => DO,      -- 8-bit Data Output
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      DOP => open,    -- 1-bit parity Output
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      ADDR => ADDR,  -- 11-bit Address Input
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      CLK => clk_inv,   --CLK,    -- Clock
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      DI => DI,      -- 8-bit Data Input
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      DIP => "1",    -- 1-bit parity Input
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      EN => EN,      -- RAM Enable Input
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      SSR => SSR,    -- Synchronous Set/Reset Input
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      WE => WE       -- Write Enable Input
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   );
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   -- End of RAMB16_S9_inst instantiation
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end Behavioral;
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