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\documentclass[a4paper,BCOR7mm,12pt,pointlessnumbers,bibtotoc]{scrartcl}
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\usepackage{amsmath,epsfig}
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\usepackage{color}
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\usepackage[hypcap=true,labelformat=simple]{subcaption}
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\renewcommand{\thesubfigure}{(\alph{subfigure})}
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\usepackage{tikz}
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\usetikzlibrary{arrows,automata}
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\usepackage{listings}
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\usepackage{enumitem}
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\newcolumntype{C}[1]{>{\centering\arraybackslash}p{#1}} % centering column type with fixed width
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\newcolumntype{R}[1]{>{\raggedleft\arraybackslash}p{#1}} % right aligned column type with fixed width
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\newcolumntype{L}[1]{>{\raggedright\arraybackslash}p{#1}} % left aligned column type with fixed width
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\newcommand{\ceil}[1]{\left\lceil #1 \right\rceil} %\left\lceil #1 \right\rceil
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\begin{document}
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%\maketitle
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\begin{center}
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\Large Efficient Booth Array Multiplier for Xilinx FPGAs\\[0.4cm]
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\large Martin Kumm \\[0.5cm]
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\large \today \\[0.5cm]
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\end{center}
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\section{Introduction}
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This IP core provides a resource efficient implementation of a Booth Array Multiplier for Xilinx FPGAs. For details about the architecture see \cite{kaz15}.
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\section{Interface}
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The top level entity is found in \verb|mult_booth_array.vhd|. The generics as well as the portare described in Table~\ref{tab:generics} and Table~\ref{tab:port}, respectively.
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\begin{table}[!h]
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\renewcommand{\arraystretch}{1.1}
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\caption{Description of the generics}
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\label{tab:generics}
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\centering
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\begin{tabular}{lccL{7cm}}
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\toprule
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Generic & Type & Default & Description\\
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\cmidrule(rl){1-1} \cmidrule(rl){2-2} \cmidrule(rl){3-3} \cmidrule(rl){4-4}
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\verb|word_size_a| & integer & 8 & Input word size operand $A$\\
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\verb|word_size_b| & integer & 8 & Input word size operand $B$\\
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\verb|sync_in_out| & boolean & false & If true, registers are placed at inputs and outputs (for timing results)\\
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\verb|use_pipelining| & boolean & true & If true, the multiplier is internally pipelined (highly recommented)\\
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\bottomrule
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\end{tabular}
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\end{table}
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\begin{table}[!h]
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\renewcommand{\arraystretch}{1.1}
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\caption{Description of the port}
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\label{tab:port}
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\centering
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\begin{tabular}{lcccL{5cm}}
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\toprule
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Generic & Direction & Type & Word Size & Description\\
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\cmidrule(rl){1-1} \cmidrule(rl){2-2} \cmidrule(rl){3-3} \cmidrule(rl){4-4} \cmidrule(rl){5-5}
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\verb|clk_i| & in & \verb|sl| & 1 & Clock input (used when \verb|use_pipelining=true| or \verb|sync_in_out=true|)\\
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\verb|rst_i| & in & \verb|sl| & 1 & Reset input (used when \verb|use_pipelining=true| or \verb|sync_in_out=true|)\\
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\verb|ce_i| & in & \verb|sl| & 1 & Clock enable input (used when \verb|use_pipelining=true| or \verb|sync_in_out=true|)\\
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\verb|a_i| & in & \verb|slv| & \verb|input_word_size| & Input operand $A$\\
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\verb|b_i| & in & \verb|slv| & \verb|input_word_size| & Input operand $B$\\
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\verb|p_o| & out & \verb|slv| & \verb|input_word_size + 2| & Product output $P=A \times B$\\
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\bottomrule
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\end{tabular}
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\end{table}
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\section{Simulation \& Test}
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For simulation and test, the testbench (\verb|tb_mult_booth_array.vhd|) was created which uses a random number generator together with assert statements to verify the designs (against a naive VHDL multiplication).
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\bibliographystyle{alpha}
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\bibliography{booth_array_multiplier}
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\end{document}
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