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-- File: generated/lfsr_37.vhd

-- Generated by MyHDL 0.9.0

-- Date: Thu Jan 11 17:29:05 2018

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

use std.textio.all;

use work.pck_myhdl_090.all;

entity lfsr_37 is

    port (

        reset: in std_logic;

        clock: in std_logic;

        lfsr_out: out unsigned(36 downto 0)

    );

end entity lfsr_37;

architecture MyHDL of lfsr_37 is

signal reg_internal: unsigned(36 downto 0);

begin

LFSR_37_LFSR_LOGIC: process (clock, reset) is

begin

    if (reset = '1') then

        reg_internal <= unsigned'"0010101000011111100110111001110110001";

    elsif rising_edge(clock) then

        if (reg_internal(0) = '1') then

            reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("1100101000000000000000000000000000000"));

        else

            reg_internal <= shift_right(reg_internal, 1);

        end if;

    end if;

end process LFSR_37_LFSR_LOGIC;

lfsr_out <= reg_internal;

end architecture MyHDL;