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-- File: generated/lfsr_512.vhd

-- Generated by MyHDL 0.9.0

-- Date: Thu Jan 11 17:29:05 2018

library IEEE;

use IEEE.std_logic_1164.all;

use IEEE.numeric_std.all;

use std.textio.all;

use work.pck_myhdl_090.all;

entity lfsr_512 is

    port (

        reset: in std_logic;

        clock: in std_logic;

        lfsr_out: out unsigned(511 downto 0)

    );

end entity lfsr_512;

architecture MyHDL of lfsr_512 is

signal reg_internal: unsigned(511 downto 0);

begin

LFSR_512_LFSR_LOGIC: process (clock, reset) is

begin

    if (reset = '1') then

        reg_internal <= unsigned'"00101010110110000010001111101100010011010110111101101000111000111100100100010010010011101110010100110001100111010101110101100100100110000111101000000101110001101001011010101001010011011111100011101010100011110111111110111010001001000100010000000111001111111111101100111110000011010110101111111100010101000110110001100000101000011100010010101011110101011100110011010010111100010010001100110000000011011011011010100000111100010100011100100110110100010000100000101001101100010110111100000010001000010110001001010001";

    elsif rising_edge(clock) then

        if (reg_internal(0) = '1') then

            reg_internal <= (shift_right(reg_internal, 1) xor unsigned'("10100100100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000"));

        else

            reg_internal <= shift_right(reg_internal, 1);

        end if;

    end if;

end process LFSR_512_LFSR_LOGIC;

lfsr_out <= reg_internal;

end architecture MyHDL;