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[/] [myhdl_lfsr/] [trunk/] [sample_modules/] [verilog/] [lfsr_129.v] - Blame information for rev 2

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// File: generated/lfsr_129.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_129 (
    reset,
    clock,
    out
);
 
 
input reset;
input clock;
output [128:0] out;
wire [128:0] out;
 
reg [128:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_129_LFSR_LOGIC
    if (reset == 1) begin
        reg_internal <= 165771121328680894633511164402659574323;
    end
    else begin
        if ((reg_internal[0] == 1)) begin
            reg_internal <= ((reg_internal >>> 1) ^ 130'h108000000000000000000000000000000);
        end
        else begin
            reg_internal <= (reg_internal >>> 1);
        end
    end
end
 
 
 
assign out = reg_internal;
 
endmodule

Line No.	Rev	Author	Line
1	2	raineys	`// File: generated/lfsr_129.v`
2			`// Generated by MyHDL 0.9.0`
3			`// Date: Thu Jan 11 17:13:37 2018`
4
5
6			`timescale 1ns/10ps
7
8			`module lfsr_129 (`
9			`reset,`
10			`clock,`
11			`out`
12			`);`
13
14
15			`input reset;`
16			`input clock;`
17			`output [128:0] out;`
18			`wire [128:0] out;`
19
20			`reg [128:0] reg_internal;`
21
22
23
24
25
26			`always @(posedge clock, posedge reset) begin: LFSR_129_LFSR_LOGIC`
27			`if (reset == 1) begin`
28			`reg_internal <= 165771121328680894633511164402659574323;`
29			`end`
30			`else begin`
31			`if ((reg_internal[0] == 1)) begin`
32			`reg_internal <= ((reg_internal >>> 1) ^ 130'h108000000000000000000000000000000);`
33			`end`
34			`else begin`
35			`reg_internal <= (reg_internal >>> 1);`
36			`end`
37			`end`
38			`end`
39
40
41
42			`assign out = reg_internal;`
43
44			`endmodule`

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[/] [myhdl_lfsr/] [trunk/] [sample_modules/] [verilog/] [lfsr_129.v] - Blame information for rev 2