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[/] [myhdl_lfsr/] [trunk/] [sample_modules/] [verilog/] [lfsr_4096.v] - Blame information for rev 2

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// File: generated/lfsr_4096.v
// Generated by MyHDL 0.9.0
// Date: Thu Jan 11 17:13:37 2018
 
 
`timescale 1ns/10ps
 
module lfsr_4096 (
    reset,
    clock,
    out
);
 
 
input reset;
input clock;
output [4095:0] out;
wire [4095:0] out;
 
reg [4095:0] reg_internal;
 
 
 
 
 
always @(posedge clock, posedge reset) begin: LFSR_4096_LFSR_LOGIC
    if (reset == 1) begin
        reg_internal <= 19786675161995628253053705232380800434658328903343356998292168946225953300793428037302970239001677760674830651775720458054924624113772218183597842481803550241221926201302051357077082169684001162000391542241713558530993325110715578585056220014798535858831872320095339866102555545012563632419484678645827097610425793979077131047660127312937281104500077807400960953413761879297939986522597775734007944684446896806698610758088994121516152549551975816142446460287852052016035382610259674715296505118815256954008561537059435924191829957392653292735338793775825348571169542109110173815608076120516909416398007952657252748545884559225008708594565784888961800976910565684568840941403243854182355510625433409614815199672747427886477123407500490862234637255616250719756581490124585186324009961029669131193616236195521612407385558794986320847153744737470135592555900835390768869135014476170916738105711106594640827051502097149231471123450163917466463380125013674989973162313737068543138214243648049567522900487996882361768751528902372004869252628217941089295340413103832318139955702514974410255599983651884659567565662772007619911691847074985021593970569804605713114183957218309344702586742095663603213115685142237419519413524260476513654747525;
    end
    else begin
        if ((reg_internal[0] == 1)) begin
            reg_internal <= ((reg_internal >>> 1) ^ 4097'hc001001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000);
        end
        else begin
            reg_internal <= (reg_internal >>> 1);
        end
    end
end
 
 
 
assign out = reg_internal;
 
endmodule

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[/] [myhdl_lfsr/] [trunk/] [sample_modules/] [verilog/] [lfsr_4096.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	raineys	`// File: generated/lfsr_4096.v`
2			`// Generated by MyHDL 0.9.0`
3			`// Date: Thu Jan 11 17:13:37 2018`
4
5
6			`timescale 1ns/10ps
7
8			`module lfsr_4096 (`
9			`reset,`
10			`clock,`
11			`out`
12			`);`
13
14
15			`input reset;`
16			`input clock;`
17			`output [4095:0] out;`
18			`wire [4095:0] out;`
19
20			`reg [4095:0] reg_internal;`
21
22
23
24
25
26			`always @(posedge clock, posedge reset) begin: LFSR_4096_LFSR_LOGIC`
27			`if (reset == 1) begin`
28			reg_internal <= 19786675161995628253053705232380800434658328903343356998292168946225953300793428037302970239001677760674830651775720458054924624113772218183597842481803550241221926201302051357077082169684001162000391542241713558530993325110715578585056220014798535858831872320095339866102555545012563632419484678645827097610425793979077131047660127312937281104500077807400960953413761879297939986522597775734007944684446896806698610758088994121516152549551975816142446460287852052016035382610259674715296505118815256954008561537059435924191829957392653292735338793775825348571169542109110173815608076120516909416398007952657252748545884559225008708594565784888961800976910565684568840941403243854182355510625433409614815199672747427886477123407500490862234637255616250719756581490124585186324009961029669131193616236195521612407385558794986320847153744737470135592555900835390768869135014476170916738105711106594640827051502097149231471123450163917466463380125013674989973162313737068543138214243648049567522900487996882361768751528902372004869252628217941089295340413103832318139955702514974410255599983651884659567565662772007619911691847074985021593970569804605713114183957218309344702586742095663603213115685142237419519413524260476513654747525;
29			`end`
30			`else begin`
31			`if ((reg_internal[0] == 1)) begin`
32			reg_internal <= ((reg_internal >>> 1) ^ 4097'hc001001000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000);
33			`end`
34			`else begin`
35			`reg_internal <= (reg_internal >>> 1);`
36			`end`
37			`end`
38			`end`
39
40
41
42			`assign out = reg_internal;`
43
44			`endmodule`