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[/] [myhdl_lfsr/] [trunk/] [sample_modules/] [verilog/] [tb_lfsr_257.v] - Blame information for rev 2

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module tb_lfsr_257;
 
reg reset;
reg clock;
wire [256:0] out;
 
initial begin
    $from_myhdl(
        reset,
        clock
    );
    $to_myhdl(
        out
    );
end
 
lfsr_257 dut(
    reset,
    clock,
    out
);
 
endmodule

Line No.	Rev	Author	Line
1	2	raineys	`module tb_lfsr_257;`
2
3			`reg reset;`
4			`reg clock;`
5			`wire [256:0] out;`
6
7			`initial begin`
8			`$from_myhdl(`
9			`reset,`
10			`clock`
11			`);`
12			`$to_myhdl(`
13			`out`
14			`);`
15			`end`
16
17			`lfsr_257 dut(`
18			`reset,`
19			`clock,`
20			`out`
21			`);`
22
23			`endmodule`

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[/] [myhdl_lfsr/] [trunk/] [sample_modules/] [verilog/] [tb_lfsr_257.v] - Blame information for rev 2