URL https://opencores.org/ocsvn/natalius_8bit_risc/natalius_8bit_risc/trunk

Subversion Repositories natalius_8bit_risc

[/] [natalius_8bit_risc/] [trunk/] [impl_prj/] [_xmsgs/] [pn_parser.xmsgs] - Blame information for rev 13

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Analyzing Verilog file \"C:/natalius/processor_core/ALU.v\" into library work

 
Analyzing Verilog file \"C:/natalius/processor_core/LIFO.v\" into library work

 
Analyzing Verilog file \"C:/natalius/processor_core/control_unit.v\" into library work

 
Analyzing Verilog file \"C:/natalius/processor_core/data_path.v\" into library work

 
Analyzing Verilog file \"C:/natalius/processor_core/instruction_memory.v\" into library work

 
Analyzing Verilog file \"C:/natalius/processor_core/natalius_processor.v\" into library work

 
Analyzing Verilog file \"C:/natalius/processor_core/regfile.v\" into library work

 
Analyzing Verilog file \"C:/natalius/processor_core/shiftbyte.v\" into library work

 

 

Line No.	Rev	Author	Line
1	13	fabioandre
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11			`Analyzing Verilog file \"C:/natalius/processor_core/ALU.v\" into library work`
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14			`Analyzing Verilog file \"C:/natalius/processor_core/LIFO.v\" into library work`
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17			`Analyzing Verilog file \"C:/natalius/processor_core/control_unit.v\" into library work`
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20			`Analyzing Verilog file \"C:/natalius/processor_core/data_path.v\" into library work`
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23			`Analyzing Verilog file \"C:/natalius/processor_core/instruction_memory.v\" into library work`
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26			`Analyzing Verilog file \"C:/natalius/processor_core/natalius_processor.v\" into library work`
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29			`Analyzing Verilog file \"C:/natalius/processor_core/regfile.v\" into library work`
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32			`Analyzing Verilog file \"C:/natalius/processor_core/shiftbyte.v\" into library work`
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Subversion Repositories natalius_8bit_risc

[/] [natalius_8bit_risc/] [trunk/] [impl_prj/] [_xmsgs/] [pn_parser.xmsgs] - Blame information for rev 13