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[/] [natalius_8bit_risc/] [trunk/] [processor_core/] [ALU.v] - Blame information for rev 5

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1 5 fabioandre 
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date:    19:05:06 05/02/2012
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// Design Name:
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// Module Name:    ALU
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// Project Name:
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// Target Devices:
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// Tool versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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module ALU(
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    input [7:0] a,
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    input [7:0] b,
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    output [7:0] result,
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    input [2:0] opalu,
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         output zero, carry
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    );
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reg [7:0] resu;
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always@*
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        case (opalu)
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                0: resu <= ~a;
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                1: resu <= a & b;
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                2: resu <= a ^ b;
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                3: resu <= a | b;
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                4: resu <= a;
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                5: resu <= a + b;
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                6: resu <= a - b;
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                default: resu <= a + 1;
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        endcase
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assign zero=(resu==0);
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assign result=resu;
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assign carry=(a<b);
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endmodule
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