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[/] [natalius_8bit_risc/] [trunk/] [processor_core/] [instruction_memory.v] - Blame information for rev 5

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Line No. Rev Author Line
1 5 fabioandre
`timescale 1ns / 1ps
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//////////////////////////////////////////////////////////////////////////////////
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// Company:       Universidad Pontificia Bolivariana
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// Engineer:      Fabio Andres Guzman Figueroa
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// 
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// Create Date:    21:03:05 05/14/2012 
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// Design Name: 
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// Module Name:    instruction_memory 
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// Project Name: 
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// Target Devices: 
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// Tool versions: 
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// Description: 
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//
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// Dependencies: 
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//
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// Revision: 
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// Revision 0.01 - File Created
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// Additional Comments: 
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//
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//////////////////////////////////////////////////////////////////////////////////
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module instruction_memory(
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    input clk,
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    input [10:0] address,
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    output reg [15:0] instruction
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    );
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   (* RAM_STYLE="BLOCK" *)
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        reg [15:0] rom [2047:0];
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   wire we;
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   initial
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      $readmemh("instructions.mem", rom, 0, 2047);
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        assign we=0;
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   always @(posedge clk)
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                if(we)
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                        rom[address]<=0;
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                else
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                        instruction <= rom[address];
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        //assign instruction = rom[address];
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endmodule

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