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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_package.vhd] - Blame information for rev 56

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1 2 zero_gravi 
-- #################################################################################################
2 
-- # << NEORV32 - Main VHDL package file >>                                                        #
3 
-- # ********************************************************************************************* #
4 
-- # BSD 3-Clause License                                                                          #
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-- #                                                                                               #
6 42 zero_gravi 
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
7 2 zero_gravi 
-- #                                                                                               #
8 
-- # Redistribution and use in source and binary forms, with or without modification, are          #
9 
-- # permitted provided that the following conditions are met:                                     #
10 
-- #                                                                                               #
11 
-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
12 
-- #    conditions and the following disclaimer.                                                   #
13 
-- #                                                                                               #
14 
-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
15 
-- #    conditions and the following disclaimer in the documentation and/or other materials        #
16 
-- #    provided with the distribution.                                                            #
17 
-- #                                                                                               #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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-- #    endorse or promote products derived from this software without specific prior written      #
20 
-- #    permission.                                                                                #
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-- #                                                                                               #
22 
-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
23 
-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
24 
-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
25 
-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
26 
-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
27 
-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
28 
-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
29 
-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
30 
-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
32 
-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
33 
-- #################################################################################################
34 
 
35 
library ieee;
36 
use ieee.std_logic_1164.all;
37 
use ieee.numeric_std.all;
38 
 
39 
package neorv32_package is
40 
 
41 36 zero_gravi 
  -- Architecture Configuration -------------------------------------------------------------
42 
  -- -------------------------------------------------------------------------------------------
43 40 zero_gravi 
  -- address space --
44 
  constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address
45 
  constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address
46 36 zero_gravi 
 
47 40 zero_gravi 
  -- (external) bus interface --
48 41 zero_gravi 
  constant bus_timeout_c     : natural := 127; -- cycles after which an *unacknowledged* bus access will timeout and trigger a bus fault exception (min 2)
49 40 zero_gravi 
  constant wb_pipe_mode_c    : boolean := false; -- *external* bus protocol: false=classic/standard wishbone mode (default), true=pipelined wishbone mode
50 
  constant xbus_big_endian_c : boolean := true; -- external memory access byte order: true=big endian (default); false=little endian
51 
 
52 
  -- CPU core --
53 56 zero_gravi 
  constant ipb_entries_c     : natural := 2; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2
54 
  constant cp_timeout_en_c   : boolean := false; -- auto-terminate pending co-processor operations after 256 cycles (for debugging only), default = false
55 
  constant dedicated_reset_c : boolean := false; -- use dedicated hardware reset value for UNCRITICAL registers (FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value)
56 40 zero_gravi 
 
57 54 zero_gravi 
  -- "critical" number of implemented PMP regions --
58 
  -- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces
59 
  -- increasing instruction fetch & data access latency by +1 cycle but also reducing critical path length
60 
  constant pmp_num_regions_critical_c : natural := 8; -- default=8
61 47 zero_gravi 
 
62 12 zero_gravi 
  -- Helper Functions -----------------------------------------------------------------------
63 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
64 
  function index_size_f(input : natural) return natural;
65 
  function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;
66 56 zero_gravi 
  function cond_sel_int_f(cond : boolean; val_t : integer; val_f : integer) return integer;
67 2 zero_gravi 
  function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector;
68 56 zero_gravi 
  function cond_sel_stdulogic_f(cond : boolean; val_t : std_ulogic; val_f : std_ulogic) return std_ulogic;
69 50 zero_gravi 
  function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string;
70 2 zero_gravi 
  function bool_to_ulogic_f(cond : boolean) return std_ulogic;
71 15 zero_gravi 
  function or_all_f(a : std_ulogic_vector) return std_ulogic;
72 
  function and_all_f(a : std_ulogic_vector) return std_ulogic;
73 
  function xor_all_f(a : std_ulogic_vector) return std_ulogic;
74 2 zero_gravi 
  function xnor_all_f(a : std_ulogic_vector) return std_ulogic;
75 6 zero_gravi 
  function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;
76 40 zero_gravi 
  function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector;
77 32 zero_gravi 
  function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector;
78 36 zero_gravi 
  function is_power_of_two_f(input : natural) return boolean;
79 40 zero_gravi 
  function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector;
80 2 zero_gravi 
 
81 56 zero_gravi 
  -- Architecture Constants (do not modify!) ------------------------------------------------
82 
  -- -------------------------------------------------------------------------------------------
83 
  constant data_width_c   : natural := 32; -- native data path width - do not change!
84 
  constant hw_version_c   : std_ulogic_vector(31 downto 0) := x"01050400"; -- no touchy!
85 
  constant archid_c       : natural := 19; -- official NEORV32 architecture ID - hands off!
86 
  constant rf_r0_is_reg_c : boolean := true; -- x0 is a *physical register* that has to be initialized to zero by the CPU
87 
  constant def_rst_val_c  : std_ulogic := cond_sel_stdulogic_f(dedicated_reset_c, '0', '-');
88 
 
89 15 zero_gravi 
  -- Internal Types -------------------------------------------------------------------------
90 
  -- -------------------------------------------------------------------------------------------
91 42 zero_gravi 
  type pmp_ctrl_if_t is array (0 to 63) of std_ulogic_vector(07 downto 0);
92 
  type pmp_addr_if_t is array (0 to 63) of std_ulogic_vector(33 downto 0);
93 49 zero_gravi 
  type cp_data_if_t  is array (0 to 7)  of std_ulogic_vector(data_width_c-1 downto 0);
94 15 zero_gravi 
 
95 23 zero_gravi 
  -- Processor-Internal Address Space Layout ------------------------------------------------
96 
  -- -------------------------------------------------------------------------------------------
97 34 zero_gravi 
  -- Internal Instruction Memory (IMEM) and Date Memory (DMEM) --
98 39 zero_gravi 
  constant imem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address
99 
  constant dmem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address
100 42 zero_gravi 
  --> internal data/instruction memory sizes are configured via top's generics
101 2 zero_gravi 
 
102 23 zero_gravi 
  -- Internal Bootloader ROM --
103 56 zero_gravi 
  constant boot_rom_base_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffff0000"; -- bootloader base address, fixed!
104 47 zero_gravi 
  constant boot_rom_size_c      : natural := 4*1024; -- module's address space in bytes
105 
  constant boot_rom_max_size_c  : natural := 32*1024; -- max module's address space in bytes, fixed!
106 23 zero_gravi 
 
107 2 zero_gravi 
  -- IO: Peripheral Devices ("IO") Area --
108 
  -- Control register(s) (including the device-enable) should be located at the base address of each device
109 56 zero_gravi 
  constant io_base_c            : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff00";
110 47 zero_gravi 
  constant io_size_c            : natural := 64*4; -- module's address space in bytes, fixed!
111 2 zero_gravi 
 
112 47 zero_gravi 
  -- Custom Functions Subsystem (CFS) --
113 56 zero_gravi 
  constant cfs_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff00"; -- base address
114 47 zero_gravi 
  constant cfs_size_c           : natural := 32*4; -- module's address space in bytes
115 56 zero_gravi 
  constant cfs_reg0_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff00";
116 
  constant cfs_reg1_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff04";
117 
  constant cfs_reg2_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff08";
118 
  constant cfs_reg3_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff0c";
119 
  constant cfs_reg4_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff10";
120 
  constant cfs_reg5_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff14";
121 
  constant cfs_reg6_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff18";
122 
  constant cfs_reg7_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff1c";
123 
  constant cfs_reg8_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff20";
124 
  constant cfs_reg9_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff24";
125 
  constant cfs_reg10_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff28";
126 
  constant cfs_reg11_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff2c";
127 
  constant cfs_reg12_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff30";
128 
  constant cfs_reg13_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff34";
129 
  constant cfs_reg14_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff38";
130 
  constant cfs_reg15_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff3c";
131 
  constant cfs_reg16_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff40";
132 
  constant cfs_reg17_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff44";
133 
  constant cfs_reg18_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff48";
134 
  constant cfs_reg19_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff4c";
135 
  constant cfs_reg20_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff50";
136 
  constant cfs_reg21_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff54";
137 
  constant cfs_reg22_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff58";
138 
  constant cfs_reg23_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff5c";
139 
  constant cfs_reg24_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff60";
140 
  constant cfs_reg25_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff64";
141 
  constant cfs_reg26_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff68";
142 
  constant cfs_reg27_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff6c";
143 
  constant cfs_reg28_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff70";
144 
  constant cfs_reg29_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff74";
145 
  constant cfs_reg30_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff78";
146 
  constant cfs_reg31_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff7c";
147 47 zero_gravi 
 
148 2 zero_gravi 
  -- General Purpose Input/Output Unit (GPIO) --
149 56 zero_gravi 
  constant gpio_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff80"; -- base address
150 47 zero_gravi 
  constant gpio_size_c          : natural := 2*4; -- module's address space in bytes
151 56 zero_gravi 
  constant gpio_in_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff80";
152 
  constant gpio_out_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff84";
153 2 zero_gravi 
 
154 30 zero_gravi 
  -- True Random Number Generator (TRNG) --
155 56 zero_gravi 
  constant trng_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff88"; -- base address
156 47 zero_gravi 
  constant trng_size_c          : natural := 1*4; -- module's address space in bytes
157 56 zero_gravi 
  constant trng_ctrl_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff88";
158 2 zero_gravi 
 
159 
  -- Watch Dog Timer (WDT) --
160 56 zero_gravi 
  constant wdt_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff8c"; -- base address
161 47 zero_gravi 
  constant wdt_size_c           : natural := 1*4; -- module's address space in bytes
162 56 zero_gravi 
  constant wdt_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff8c";
163 2 zero_gravi 
 
164 
  -- Machine System Timer (MTIME) --
165 56 zero_gravi 
  constant mtime_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff90"; -- base address
166 47 zero_gravi 
  constant mtime_size_c         : natural := 4*4; -- module's address space in bytes
167 56 zero_gravi 
  constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff90";
168 
  constant mtime_time_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff94";
169 
  constant mtime_cmp_lo_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff98";
170 
  constant mtime_cmp_hi_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff9c";
171 2 zero_gravi 
 
172 50 zero_gravi 
  -- Universal Asynchronous Receiver/Transmitter 0 (UART0), primary UART --
173 56 zero_gravi 
  constant uart0_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa0"; -- base address
174 50 zero_gravi 
  constant uart0_size_c         : natural := 2*4; -- module's address space in bytes
175 56 zero_gravi 
  constant uart0_ctrl_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa0";
176 
  constant uart0_rtx_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa4";
177 2 zero_gravi 
 
178 
  -- Serial Peripheral Interface (SPI) --
179 56 zero_gravi 
  constant spi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa8"; -- base address
180 47 zero_gravi 
  constant spi_size_c           : natural := 2*4; -- module's address space in bytes
181 56 zero_gravi 
  constant spi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa8";
182 
  constant spi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffac";
183 2 zero_gravi 
 
184 
  -- Two Wire Interface (TWI) --
185 56 zero_gravi 
  constant twi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb0"; -- base address
186 47 zero_gravi 
  constant twi_size_c           : natural := 2*4; -- module's address space in bytes
187 56 zero_gravi 
  constant twi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb0";
188 
  constant twi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb4";
189 2 zero_gravi 
 
190 
  -- Pulse-Width Modulation Controller (PWM) --
191 56 zero_gravi 
  constant pwm_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb8"; -- base address
192 47 zero_gravi 
  constant pwm_size_c           : natural := 2*4; -- module's address space in bytes
193 56 zero_gravi 
  constant pwm_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb8";
194 
  constant pwm_duty_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffbc";
195 2 zero_gravi 
 
196 49 zero_gravi 
  -- Numerically-Controlled Oscillator (NCO) --
197 56 zero_gravi 
  constant nco_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc0"; -- base address
198 49 zero_gravi 
  constant nco_size_c           : natural := 4*4; -- module's address space in bytes
199 56 zero_gravi 
  constant nco_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc0";
200 
  constant nco_ch0_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc4";
201 
  constant nco_ch1_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc8";
202 
  constant nco_ch2_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffcc";
203 49 zero_gravi 
 
204 50 zero_gravi 
  -- Universal Asynchronous Receiver/Transmitter 1 (UART1), secondary UART --
205 56 zero_gravi 
  constant uart1_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd0"; -- base address
206 50 zero_gravi 
  constant uart1_size_c         : natural := 2*4; -- module's address space in bytes
207 56 zero_gravi 
  constant uart1_ctrl_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd0";
208 
  constant uart1_rtx_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd4";
209 50 zero_gravi 
 
210 52 zero_gravi 
  -- Smart LED (WS2811/WS2812) Interface (NEOLED) --
211 56 zero_gravi 
  constant neoled_base_c        : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd8"; -- base address
212 52 zero_gravi 
  constant neoled_size_c        : natural := 2*4; -- module's address space in bytes
213 56 zero_gravi 
  constant neoled_ctrl_addr_c   : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd8";
214 
  constant neoled_data_addr_c   : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffdc";
215 12 zero_gravi 
 
216 23 zero_gravi 
  -- System Information Memory (SYSINFO) --
217 56 zero_gravi 
  constant sysinfo_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffe0"; -- base address
218 47 zero_gravi 
  constant sysinfo_size_c       : natural := 8*4; -- module's address space in bytes
219 12 zero_gravi 
 
220 2 zero_gravi 
  -- Main Control Bus -----------------------------------------------------------------------
221 
  -- -------------------------------------------------------------------------------------------
222 
  -- register file --
223 49 zero_gravi 
  constant ctrl_rf_in_mux_c     : natural :=  0; -- input source select lsb (0=MEM, 1=ALU)
224 
  constant ctrl_rf_rs1_adr0_c   : natural :=  1; -- source register 1 address bit 0
225 
  constant ctrl_rf_rs1_adr1_c   : natural :=  2; -- source register 1 address bit 1
226 
  constant ctrl_rf_rs1_adr2_c   : natural :=  3; -- source register 1 address bit 2
227 
  constant ctrl_rf_rs1_adr3_c   : natural :=  4; -- source register 1 address bit 3
228 
  constant ctrl_rf_rs1_adr4_c   : natural :=  5; -- source register 1 address bit 4
229 
  constant ctrl_rf_rs2_adr0_c   : natural :=  6; -- source register 2 address bit 0
230 
  constant ctrl_rf_rs2_adr1_c   : natural :=  7; -- source register 2 address bit 1
231 
  constant ctrl_rf_rs2_adr2_c   : natural :=  8; -- source register 2 address bit 2
232 
  constant ctrl_rf_rs2_adr3_c   : natural :=  9; -- source register 2 address bit 3
233 
  constant ctrl_rf_rs2_adr4_c   : natural := 10; -- source register 2 address bit 4
234 
  constant ctrl_rf_rd_adr0_c    : natural := 11; -- destiantion register address bit 0
235 
  constant ctrl_rf_rd_adr1_c    : natural := 12; -- destiantion register address bit 1
236 
  constant ctrl_rf_rd_adr2_c    : natural := 13; -- destiantion register address bit 2
237 
  constant ctrl_rf_rd_adr3_c    : natural := 14; -- destiantion register address bit 3
238 
  constant ctrl_rf_rd_adr4_c    : natural := 15; -- destiantion register address bit 4
239 
  constant ctrl_rf_wb_en_c      : natural := 16; -- write back enable
240 
  constant ctrl_rf_r0_we_c      : natural := 17; -- force write access and force rd=r0
241 2 zero_gravi 
  -- alu --
242 49 zero_gravi 
  constant ctrl_alu_arith_c     : natural := 18; -- ALU arithmetic command
243 
  constant ctrl_alu_logic0_c    : natural := 19; -- ALU logic command bit 0
244 
  constant ctrl_alu_logic1_c    : natural := 20; -- ALU logic command bit 1
245 
  constant ctrl_alu_func0_c     : natural := 21; -- ALU function select command bit 0
246 
  constant ctrl_alu_func1_c     : natural := 22; -- ALU function select command bit 1
247 
  constant ctrl_alu_addsub_c    : natural := 23; -- 0=ADD, 1=SUB
248 
  constant ctrl_alu_opa_mux_c   : natural := 24; -- operand A select (0=rs1, 1=PC)
249 
  constant ctrl_alu_opb_mux_c   : natural := 25; -- operand B select (0=rs2, 1=IMM)
250 
  constant ctrl_alu_unsigned_c  : natural := 26; -- is unsigned ALU operation
251 
  constant ctrl_alu_shift_dir_c : natural := 27; -- shift direction (0=left, 1=right)
252 
  constant ctrl_alu_shift_ar_c  : natural := 28; -- is arithmetic shift
253 2 zero_gravi 
  -- bus interface --
254 49 zero_gravi 
  constant ctrl_bus_size_lsb_c  : natural := 29; -- transfer size lsb (00=byte, 01=half-word)
255 
  constant ctrl_bus_size_msb_c  : natural := 30; -- transfer size msb (10=word, 11=?)
256 
  constant ctrl_bus_rd_c        : natural := 31; -- read data request
257 
  constant ctrl_bus_wr_c        : natural := 32; -- write data request
258 
  constant ctrl_bus_if_c        : natural := 33; -- instruction fetch request
259 
  constant ctrl_bus_mo_we_c     : natural := 34; -- memory address and data output register write enable
260 
  constant ctrl_bus_mi_we_c     : natural := 35; -- memory data input register write enable
261 53 zero_gravi 
  constant ctrl_bus_unsigned_c  : natural := 36; -- is unsigned load
262 
  constant ctrl_bus_ierr_ack_c  : natural := 37; -- acknowledge instruction fetch bus exceptions
263 
  constant ctrl_bus_derr_ack_c  : natural := 38; -- acknowledge data access bus exceptions
264 
  constant ctrl_bus_fence_c     : natural := 39; -- executed fence operation
265 
  constant ctrl_bus_fencei_c    : natural := 40; -- executed fencei operation
266 
  constant ctrl_bus_excl_c      : natural := 41; -- exclusive bus access
267 26 zero_gravi 
  -- co-processors --
268 53 zero_gravi 
  constant ctrl_cp_id_lsb_c     : natural := 42; -- cp select ID lsb
269 56 zero_gravi 
  constant ctrl_cp_id_hsb_c     : natural := 43; -- cp select ID
270 53 zero_gravi 
  constant ctrl_cp_id_msb_c     : natural := 44; -- cp select ID msb
271 36 zero_gravi 
  -- current privilege level --
272 53 zero_gravi 
  constant ctrl_priv_lvl_lsb_c  : natural := 45; -- privilege level lsb
273 
  constant ctrl_priv_lvl_msb_c  : natural := 46; -- privilege level msb
274 44 zero_gravi 
  -- instruction's control blocks (used by cpu co-processors) --
275 53 zero_gravi 
  constant ctrl_ir_funct3_0_c   : natural := 47; -- funct3 bit 0
276 
  constant ctrl_ir_funct3_1_c   : natural := 48; -- funct3 bit 1
277 
  constant ctrl_ir_funct3_2_c   : natural := 49; -- funct3 bit 2
278 
  constant ctrl_ir_funct12_0_c  : natural := 50; -- funct12 bit 0
279 
  constant ctrl_ir_funct12_1_c  : natural := 51; -- funct12 bit 1
280 
  constant ctrl_ir_funct12_2_c  : natural := 52; -- funct12 bit 2
281 
  constant ctrl_ir_funct12_3_c  : natural := 53; -- funct12 bit 3
282 
  constant ctrl_ir_funct12_4_c  : natural := 54; -- funct12 bit 4
283 
  constant ctrl_ir_funct12_5_c  : natural := 55; -- funct12 bit 5
284 
  constant ctrl_ir_funct12_6_c  : natural := 56; -- funct12 bit 6
285 
  constant ctrl_ir_funct12_7_c  : natural := 57; -- funct12 bit 7
286 
  constant ctrl_ir_funct12_8_c  : natural := 58; -- funct12 bit 8
287 
  constant ctrl_ir_funct12_9_c  : natural := 59; -- funct12 bit 9
288 
  constant ctrl_ir_funct12_10_c : natural := 60; -- funct12 bit 10
289 
  constant ctrl_ir_funct12_11_c : natural := 61; -- funct12 bit 11
290 
  constant ctrl_ir_opcode7_0_c  : natural := 62; -- opcode7 bit 0
291 
  constant ctrl_ir_opcode7_1_c  : natural := 63; -- opcode7 bit 1
292 
  constant ctrl_ir_opcode7_2_c  : natural := 64; -- opcode7 bit 2
293 
  constant ctrl_ir_opcode7_3_c  : natural := 65; -- opcode7 bit 3
294 
  constant ctrl_ir_opcode7_4_c  : natural := 66; -- opcode7 bit 4
295 
  constant ctrl_ir_opcode7_5_c  : natural := 67; -- opcode7 bit 5
296 
  constant ctrl_ir_opcode7_6_c  : natural := 68; -- opcode7 bit 6
297 47 zero_gravi 
  -- CPU status --
298 53 zero_gravi 
  constant ctrl_sleep_c         : natural := 69; -- set when CPU is in sleep mode
299 2 zero_gravi 
  -- control bus size --
300 53 zero_gravi 
  constant ctrl_width_c         : natural := 70; -- control bus size
301 2 zero_gravi 
 
302 47 zero_gravi 
  -- Comparator Bus -------------------------------------------------------------------------
303 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
304 47 zero_gravi 
  constant cmp_equal_c : natural := 0;
305 
  constant cmp_less_c  : natural := 1; -- for signed and unsigned comparisons
306 2 zero_gravi 
 
307 
  -- RISC-V Opcode Layout -------------------------------------------------------------------
308 
  -- -------------------------------------------------------------------------------------------
309 
  constant instr_opcode_lsb_c  : natural :=  0; -- opcode bit 0
310 
  constant instr_opcode_msb_c  : natural :=  6; -- opcode bit 6
311 
  constant instr_rd_lsb_c      : natural :=  7; -- destination register address bit 0
312 
  constant instr_rd_msb_c      : natural := 11; -- destination register address bit 4
313 
  constant instr_funct3_lsb_c  : natural := 12; -- funct3 bit 0
314 
  constant instr_funct3_msb_c  : natural := 14; -- funct3 bit 2
315 
  constant instr_rs1_lsb_c     : natural := 15; -- source register 1 address bit 0
316 
  constant instr_rs1_msb_c     : natural := 19; -- source register 1 address bit 4
317 
  constant instr_rs2_lsb_c     : natural := 20; -- source register 2 address bit 0
318 
  constant instr_rs2_msb_c     : natural := 24; -- source register 2 address bit 4
319 
  constant instr_funct7_lsb_c  : natural := 25; -- funct7 bit 0
320 
  constant instr_funct7_msb_c  : natural := 31; -- funct7 bit 6
321 
  constant instr_funct12_lsb_c : natural := 20; -- funct12 bit 0
322 
  constant instr_funct12_msb_c : natural := 31; -- funct12 bit 11
323 
  constant instr_imm12_lsb_c   : natural := 20; -- immediate12 bit 0
324 
  constant instr_imm12_msb_c   : natural := 31; -- immediate12 bit 11
325 
  constant instr_imm20_lsb_c   : natural := 12; -- immediate20 bit 0
326 
  constant instr_imm20_msb_c   : natural := 31; -- immediate20 bit 21
327 
  constant instr_csr_id_lsb_c  : natural := 20; -- csr select bit 0
328 
  constant instr_csr_id_msb_c  : natural := 31; -- csr select bit 11
329 39 zero_gravi 
  constant instr_funct5_lsb_c  : natural := 27; -- funct5 select bit 0
330 
  constant instr_funct5_msb_c  : natural := 31; -- funct5 select bit 4
331 2 zero_gravi 
 
332 
  -- RISC-V Opcodes -------------------------------------------------------------------------
333 
  -- -------------------------------------------------------------------------------------------
334 
  -- alu --
335 
  constant opcode_lui_c    : std_ulogic_vector(6 downto 0) := "0110111"; -- load upper immediate
336 
  constant opcode_auipc_c  : std_ulogic_vector(6 downto 0) := "0010111"; -- add upper immediate to PC
337 
  constant opcode_alui_c   : std_ulogic_vector(6 downto 0) := "0010011"; -- ALU operation with immediate (operation via funct3 and funct7)
338 
  constant opcode_alu_c    : std_ulogic_vector(6 downto 0) := "0110011"; -- ALU operation (operation via funct3 and funct7)
339 
  -- control flow --
340 
  constant opcode_jal_c    : std_ulogic_vector(6 downto 0) := "1101111"; -- jump and link
341 29 zero_gravi 
  constant opcode_jalr_c   : std_ulogic_vector(6 downto 0) := "1100111"; -- jump and link with register
342 2 zero_gravi 
  constant opcode_branch_c : std_ulogic_vector(6 downto 0) := "1100011"; -- branch (condition set via funct3)
343 
  -- memory access --
344 
  constant opcode_load_c   : std_ulogic_vector(6 downto 0) := "0000011"; -- load (data type via funct3)
345 
  constant opcode_store_c  : std_ulogic_vector(6 downto 0) := "0100011"; -- store (data type via funct3)
346 
  -- system/csr --
347 8 zero_gravi 
  constant opcode_fence_c  : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i
348 2 zero_gravi 
  constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)
349 52 zero_gravi 
  -- atomic memory access (A) --
350 39 zero_gravi 
  constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension)
351 53 zero_gravi 
  -- floating point operations (Zfinx-only) (F/D/H/Q) --
352 
  constant opcode_fop_c    : std_ulogic_vector(6 downto 0) := "1010011"; -- dual/single opearand instruction
353 2 zero_gravi 
 
354 
  -- RISC-V Funct3 --------------------------------------------------------------------------
355 
  -- -------------------------------------------------------------------------------------------
356 
  -- control flow --
357 
  constant funct3_beq_c    : std_ulogic_vector(2 downto 0) := "000"; -- branch if equal
358 
  constant funct3_bne_c    : std_ulogic_vector(2 downto 0) := "001"; -- branch if not equal
359 
  constant funct3_blt_c    : std_ulogic_vector(2 downto 0) := "100"; -- branch if less than
360 
  constant funct3_bge_c    : std_ulogic_vector(2 downto 0) := "101"; -- branch if greater than or equal
361 
  constant funct3_bltu_c   : std_ulogic_vector(2 downto 0) := "110"; -- branch if less than (unsigned)
362 
  constant funct3_bgeu_c   : std_ulogic_vector(2 downto 0) := "111"; -- branch if greater than or equal (unsigned)
363 
  -- memory access --
364 
  constant funct3_lb_c     : std_ulogic_vector(2 downto 0) := "000"; -- load byte
365 
  constant funct3_lh_c     : std_ulogic_vector(2 downto 0) := "001"; -- load half word
366 
  constant funct3_lw_c     : std_ulogic_vector(2 downto 0) := "010"; -- load word
367 
  constant funct3_lbu_c    : std_ulogic_vector(2 downto 0) := "100"; -- load byte (unsigned)
368 
  constant funct3_lhu_c    : std_ulogic_vector(2 downto 0) := "101"; -- load half word (unsigned)
369 
  constant funct3_sb_c     : std_ulogic_vector(2 downto 0) := "000"; -- store byte
370 
  constant funct3_sh_c     : std_ulogic_vector(2 downto 0) := "001"; -- store half word
371 
  constant funct3_sw_c     : std_ulogic_vector(2 downto 0) := "010"; -- store word
372 
  -- alu --
373 
  constant funct3_subadd_c : std_ulogic_vector(2 downto 0) := "000"; -- sub/add via funct7
374 
  constant funct3_sll_c    : std_ulogic_vector(2 downto 0) := "001"; -- shift logical left
375 
  constant funct3_slt_c    : std_ulogic_vector(2 downto 0) := "010"; -- set on less
376 
  constant funct3_sltu_c   : std_ulogic_vector(2 downto 0) := "011"; -- set on less unsigned
377 
  constant funct3_xor_c    : std_ulogic_vector(2 downto 0) := "100"; -- xor
378 
  constant funct3_sr_c     : std_ulogic_vector(2 downto 0) := "101"; -- shift right via funct7
379 
  constant funct3_or_c     : std_ulogic_vector(2 downto 0) := "110"; -- or
380 
  constant funct3_and_c    : std_ulogic_vector(2 downto 0) := "111"; -- and
381 
  -- system/csr --
382 
  constant funct3_env_c    : std_ulogic_vector(2 downto 0) := "000"; -- ecall, ebreak, mret, wfi
383 
  constant funct3_csrrw_c  : std_ulogic_vector(2 downto 0) := "001"; -- atomic r/w
384 
  constant funct3_csrrs_c  : std_ulogic_vector(2 downto 0) := "010"; -- atomic read & set bit
385 
  constant funct3_csrrc_c  : std_ulogic_vector(2 downto 0) := "011"; -- atomic read & clear bit
386 
  constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- atomic r/w immediate
387 
  constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- atomic read & set bit immediate
388 
  constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate
389 8 zero_gravi 
  -- fence --
390 
  constant funct3_fence_c  : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)
391 
  constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instructon stream sync
392 2 zero_gravi 
 
393 39 zero_gravi 
  -- RISC-V Funct12 -------------------------------------------------------------------------
394 11 zero_gravi 
  -- -------------------------------------------------------------------------------------------
395 
  -- system --
396 
  constant funct12_ecall_c  : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL
397 
  constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK
398 
  constant funct12_mret_c   : std_ulogic_vector(11 downto 0) := x"302"; -- MRET
399 
  constant funct12_wfi_c    : std_ulogic_vector(11 downto 0) := x"105"; -- WFI
400 
 
401 39 zero_gravi 
  -- RISC-V Funct5 --------------------------------------------------------------------------
402 
  -- -------------------------------------------------------------------------------------------
403 
  -- atomic operations --
404 
  constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- LR
405 
  constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"; -- SC
406 
 
407 54 zero_gravi 
  -- RISC-V Floating-Point Stuff ------------------------------------------------------------
408 52 zero_gravi 
  -- -------------------------------------------------------------------------------------------
409 54 zero_gravi 
  -- formats --
410 
  constant float_single_c : std_ulogic_vector(1 downto 0) := "00"; -- single-precision (32-bit)
411 
  constant float_double_c : std_ulogic_vector(1 downto 0) := "01"; -- double-precision (64-bit)
412 
  constant float_half_c   : std_ulogic_vector(1 downto 0) := "10"; -- half-precision (16-bit)
413 
  constant float_quad_c   : std_ulogic_vector(1 downto 0) := "11"; -- quad-precision (128-bit)
414 52 zero_gravi 
 
415 54 zero_gravi 
  -- number class flags --
416 
  constant fp_class_neg_inf_c    : natural := 0; -- negative infinity
417 
  constant fp_class_neg_norm_c   : natural := 1; -- negative normal number
418 
  constant fp_class_neg_denorm_c : natural := 2; -- negative subnormal number
419 
  constant fp_class_neg_zero_c   : natural := 3; -- negative zero
420 
  constant fp_class_pos_zero_c   : natural := 4; -- positive zero
421 
  constant fp_class_pos_denorm_c : natural := 5; -- positive subnormal number
422 
  constant fp_class_pos_norm_c   : natural := 6; -- positive normal number
423 
  constant fp_class_pos_inf_c    : natural := 7; -- positive infinity
424 
  constant fp_class_snan_c       : natural := 8; -- signaling NaN (sNaN)
425 
  constant fp_class_qnan_c       : natural := 9; -- quiet NaN (qNaN)
426 
 
427 
  -- exception flags --
428 
  constant fp_exc_nv_c : natural := 0; -- invalid operation
429 
  constant fp_exc_dz_c : natural := 1; -- divide by zero
430 
  constant fp_exc_of_c : natural := 2; -- overflow
431 
  constant fp_exc_uf_c : natural := 3; -- underflow
432 
  constant fp_exc_nx_c : natural := 4; -- inexact
433 
 
434 
  -- special values (single-precision) --
435 
  constant fp_single_qnan_c     : std_ulogic_vector(31 downto 0) := x"7fc00000"; -- quiet NaN
436 
  constant fp_single_snan_c     : std_ulogic_vector(31 downto 0) := x"7fa00000"; -- signaling NaN
437 
  constant fp_single_pos_inf_c  : std_ulogic_vector(31 downto 0) := x"7f800000"; -- positive infinity
438 
  constant fp_single_neg_inf_c  : std_ulogic_vector(31 downto 0) := x"ff800000"; -- negative infinity
439 
  constant fp_single_pos_zero_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- positive zero
440 
  constant fp_single_neg_zero_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- negative zero
441 
 
442 29 zero_gravi 
  -- RISC-V CSR Addresses -------------------------------------------------------------------
443 
  -- -------------------------------------------------------------------------------------------
444 56 zero_gravi 
  -- <<< standard read/write CSRs >>> --
445 
  -- user floating-point CSRs --
446 52 zero_gravi 
  constant csr_class_float_c    : std_ulogic_vector(07 downto 0) := x"00"; -- floating point
447 
  constant csr_fflags_c         : std_ulogic_vector(11 downto 0) := x"001";
448 
  constant csr_frm_c            : std_ulogic_vector(11 downto 0) := x"002";
449 
  constant csr_fcsr_c           : std_ulogic_vector(11 downto 0) := x"003";
450 56 zero_gravi 
  -- machine trap setup --
451 
  constant csr_class_setup_c    : std_ulogic_vector(07 downto 0) := x"30"; -- trap setup
452 42 zero_gravi 
  constant csr_mstatus_c        : std_ulogic_vector(11 downto 0) := x"300";
453 
  constant csr_misa_c           : std_ulogic_vector(11 downto 0) := x"301";
454 
  constant csr_mie_c            : std_ulogic_vector(11 downto 0) := x"304";
455 
  constant csr_mtvec_c          : std_ulogic_vector(11 downto 0) := x"305";
456 
  constant csr_mcounteren_c     : std_ulogic_vector(11 downto 0) := x"306";
457 
  constant csr_mstatush_c       : std_ulogic_vector(11 downto 0) := x"310";
458 56 zero_gravi 
  -- machine counter setup --
459 
  constant csr_cnt_setup_c      : std_ulogic_vector(06 downto 0) := x"3" & "001"; -- counter setup
460 42 zero_gravi 
  constant csr_mcountinhibit_c  : std_ulogic_vector(11 downto 0) := x"320";
461 
  constant csr_mhpmevent3_c     : std_ulogic_vector(11 downto 0) := x"323";
462 
  constant csr_mhpmevent4_c     : std_ulogic_vector(11 downto 0) := x"324";
463 
  constant csr_mhpmevent5_c     : std_ulogic_vector(11 downto 0) := x"325";
464 
  constant csr_mhpmevent6_c     : std_ulogic_vector(11 downto 0) := x"326";
465 
  constant csr_mhpmevent7_c     : std_ulogic_vector(11 downto 0) := x"327";
466 
  constant csr_mhpmevent8_c     : std_ulogic_vector(11 downto 0) := x"328";
467 
  constant csr_mhpmevent9_c     : std_ulogic_vector(11 downto 0) := x"329";
468 
  constant csr_mhpmevent10_c    : std_ulogic_vector(11 downto 0) := x"32a";
469 
  constant csr_mhpmevent11_c    : std_ulogic_vector(11 downto 0) := x"32b";
470 
  constant csr_mhpmevent12_c    : std_ulogic_vector(11 downto 0) := x"32c";
471 
  constant csr_mhpmevent13_c    : std_ulogic_vector(11 downto 0) := x"32d";
472 
  constant csr_mhpmevent14_c    : std_ulogic_vector(11 downto 0) := x"32e";
473 
  constant csr_mhpmevent15_c    : std_ulogic_vector(11 downto 0) := x"32f";
474 
  constant csr_mhpmevent16_c    : std_ulogic_vector(11 downto 0) := x"330";
475 
  constant csr_mhpmevent17_c    : std_ulogic_vector(11 downto 0) := x"331";
476 
  constant csr_mhpmevent18_c    : std_ulogic_vector(11 downto 0) := x"332";
477 
  constant csr_mhpmevent19_c    : std_ulogic_vector(11 downto 0) := x"333";
478 
  constant csr_mhpmevent20_c    : std_ulogic_vector(11 downto 0) := x"334";
479 
  constant csr_mhpmevent21_c    : std_ulogic_vector(11 downto 0) := x"335";
480 
  constant csr_mhpmevent22_c    : std_ulogic_vector(11 downto 0) := x"336";
481 
  constant csr_mhpmevent23_c    : std_ulogic_vector(11 downto 0) := x"337";
482 
  constant csr_mhpmevent24_c    : std_ulogic_vector(11 downto 0) := x"338";
483 
  constant csr_mhpmevent25_c    : std_ulogic_vector(11 downto 0) := x"339";
484 
  constant csr_mhpmevent26_c    : std_ulogic_vector(11 downto 0) := x"33a";
485 
  constant csr_mhpmevent27_c    : std_ulogic_vector(11 downto 0) := x"33b";
486 
  constant csr_mhpmevent28_c    : std_ulogic_vector(11 downto 0) := x"33c";
487 
  constant csr_mhpmevent29_c    : std_ulogic_vector(11 downto 0) := x"33d";
488 
  constant csr_mhpmevent30_c    : std_ulogic_vector(11 downto 0) := x"33e";
489 
  constant csr_mhpmevent31_c    : std_ulogic_vector(11 downto 0) := x"33f";
490 56 zero_gravi 
  -- machine trap handling --
491 52 zero_gravi 
  constant csr_class_trap_c     : std_ulogic_vector(07 downto 0) := x"34"; -- machine trap handling
492 42 zero_gravi 
  constant csr_mscratch_c       : std_ulogic_vector(11 downto 0) := x"340";
493 
  constant csr_mepc_c           : std_ulogic_vector(11 downto 0) := x"341";
494 
  constant csr_mcause_c         : std_ulogic_vector(11 downto 0) := x"342";
495 
  constant csr_mtval_c          : std_ulogic_vector(11 downto 0) := x"343";
496 
  constant csr_mip_c            : std_ulogic_vector(11 downto 0) := x"344";
497 56 zero_gravi 
  -- physical memory protection - configuration --
498 52 zero_gravi 
  constant csr_class_pmpcfg_c   : std_ulogic_vector(07 downto 0) := x"3a"; -- pmp configuration
499 42 zero_gravi 
  constant csr_pmpcfg0_c        : std_ulogic_vector(11 downto 0) := x"3a0";
500 
  constant csr_pmpcfg1_c        : std_ulogic_vector(11 downto 0) := x"3a1";
501 
  constant csr_pmpcfg2_c        : std_ulogic_vector(11 downto 0) := x"3a2";
502 
  constant csr_pmpcfg3_c        : std_ulogic_vector(11 downto 0) := x"3a3";
503 
  constant csr_pmpcfg4_c        : std_ulogic_vector(11 downto 0) := x"3a4";
504 
  constant csr_pmpcfg5_c        : std_ulogic_vector(11 downto 0) := x"3a5";
505 
  constant csr_pmpcfg6_c        : std_ulogic_vector(11 downto 0) := x"3a6";
506 
  constant csr_pmpcfg7_c        : std_ulogic_vector(11 downto 0) := x"3a7";
507 
  constant csr_pmpcfg8_c        : std_ulogic_vector(11 downto 0) := x"3a8";
508 
  constant csr_pmpcfg9_c        : std_ulogic_vector(11 downto 0) := x"3a9";
509 
  constant csr_pmpcfg10_c       : std_ulogic_vector(11 downto 0) := x"3aa";
510 
  constant csr_pmpcfg11_c       : std_ulogic_vector(11 downto 0) := x"3ab";
511 
  constant csr_pmpcfg12_c       : std_ulogic_vector(11 downto 0) := x"3ac";
512 
  constant csr_pmpcfg13_c       : std_ulogic_vector(11 downto 0) := x"3ad";
513 
  constant csr_pmpcfg14_c       : std_ulogic_vector(11 downto 0) := x"3ae";
514 
  constant csr_pmpcfg15_c       : std_ulogic_vector(11 downto 0) := x"3af";
515 56 zero_gravi 
  -- physical memory protection - address --
516 42 zero_gravi 
  constant csr_pmpaddr0_c       : std_ulogic_vector(11 downto 0) := x"3b0";
517 
  constant csr_pmpaddr1_c       : std_ulogic_vector(11 downto 0) := x"3b1";
518 
  constant csr_pmpaddr2_c       : std_ulogic_vector(11 downto 0) := x"3b2";
519 
  constant csr_pmpaddr3_c       : std_ulogic_vector(11 downto 0) := x"3b3";
520 
  constant csr_pmpaddr4_c       : std_ulogic_vector(11 downto 0) := x"3b4";
521 
  constant csr_pmpaddr5_c       : std_ulogic_vector(11 downto 0) := x"3b5";
522 
  constant csr_pmpaddr6_c       : std_ulogic_vector(11 downto 0) := x"3b6";
523 
  constant csr_pmpaddr7_c       : std_ulogic_vector(11 downto 0) := x"3b7";
524 
  constant csr_pmpaddr8_c       : std_ulogic_vector(11 downto 0) := x"3b8";
525 
  constant csr_pmpaddr9_c       : std_ulogic_vector(11 downto 0) := x"3b9";
526 
  constant csr_pmpaddr10_c      : std_ulogic_vector(11 downto 0) := x"3ba";
527 
  constant csr_pmpaddr11_c      : std_ulogic_vector(11 downto 0) := x"3bb";
528 
  constant csr_pmpaddr12_c      : std_ulogic_vector(11 downto 0) := x"3bc";
529 
  constant csr_pmpaddr13_c      : std_ulogic_vector(11 downto 0) := x"3bd";
530 
  constant csr_pmpaddr14_c      : std_ulogic_vector(11 downto 0) := x"3be";
531 
  constant csr_pmpaddr15_c      : std_ulogic_vector(11 downto 0) := x"3bf";
532 
  constant csr_pmpaddr16_c      : std_ulogic_vector(11 downto 0) := x"3c0";
533 
  constant csr_pmpaddr17_c      : std_ulogic_vector(11 downto 0) := x"3c1";
534 
  constant csr_pmpaddr18_c      : std_ulogic_vector(11 downto 0) := x"3c2";
535 
  constant csr_pmpaddr19_c      : std_ulogic_vector(11 downto 0) := x"3c3";
536 
  constant csr_pmpaddr20_c      : std_ulogic_vector(11 downto 0) := x"3c4";
537 
  constant csr_pmpaddr21_c      : std_ulogic_vector(11 downto 0) := x"3c5";
538 
  constant csr_pmpaddr22_c      : std_ulogic_vector(11 downto 0) := x"3c6";
539 
  constant csr_pmpaddr23_c      : std_ulogic_vector(11 downto 0) := x"3c7";
540 
  constant csr_pmpaddr24_c      : std_ulogic_vector(11 downto 0) := x"3c8";
541 
  constant csr_pmpaddr25_c      : std_ulogic_vector(11 downto 0) := x"3c9";
542 
  constant csr_pmpaddr26_c      : std_ulogic_vector(11 downto 0) := x"3ca";
543 
  constant csr_pmpaddr27_c      : std_ulogic_vector(11 downto 0) := x"3cb";
544 
  constant csr_pmpaddr28_c      : std_ulogic_vector(11 downto 0) := x"3cc";
545 
  constant csr_pmpaddr29_c      : std_ulogic_vector(11 downto 0) := x"3cd";
546 
  constant csr_pmpaddr30_c      : std_ulogic_vector(11 downto 0) := x"3ce";
547 
  constant csr_pmpaddr31_c      : std_ulogic_vector(11 downto 0) := x"3cf";
548 
  constant csr_pmpaddr32_c      : std_ulogic_vector(11 downto 0) := x"3d0";
549 
  constant csr_pmpaddr33_c      : std_ulogic_vector(11 downto 0) := x"3d1";
550 
  constant csr_pmpaddr34_c      : std_ulogic_vector(11 downto 0) := x"3d2";
551 
  constant csr_pmpaddr35_c      : std_ulogic_vector(11 downto 0) := x"3d3";
552 
  constant csr_pmpaddr36_c      : std_ulogic_vector(11 downto 0) := x"3d4";
553 
  constant csr_pmpaddr37_c      : std_ulogic_vector(11 downto 0) := x"3d5";
554 
  constant csr_pmpaddr38_c      : std_ulogic_vector(11 downto 0) := x"3d6";
555 
  constant csr_pmpaddr39_c      : std_ulogic_vector(11 downto 0) := x"3d7";
556 
  constant csr_pmpaddr40_c      : std_ulogic_vector(11 downto 0) := x"3d8";
557 
  constant csr_pmpaddr41_c      : std_ulogic_vector(11 downto 0) := x"3d9";
558 
  constant csr_pmpaddr42_c      : std_ulogic_vector(11 downto 0) := x"3da";
559 
  constant csr_pmpaddr43_c      : std_ulogic_vector(11 downto 0) := x"3db";
560 
  constant csr_pmpaddr44_c      : std_ulogic_vector(11 downto 0) := x"3dc";
561 
  constant csr_pmpaddr45_c      : std_ulogic_vector(11 downto 0) := x"3dd";
562 
  constant csr_pmpaddr46_c      : std_ulogic_vector(11 downto 0) := x"3de";
563 
  constant csr_pmpaddr47_c      : std_ulogic_vector(11 downto 0) := x"3df";
564 
  constant csr_pmpaddr48_c      : std_ulogic_vector(11 downto 0) := x"3e0";
565 
  constant csr_pmpaddr49_c      : std_ulogic_vector(11 downto 0) := x"3e1";
566 
  constant csr_pmpaddr50_c      : std_ulogic_vector(11 downto 0) := x"3e2";
567 
  constant csr_pmpaddr51_c      : std_ulogic_vector(11 downto 0) := x"3e3";
568 
  constant csr_pmpaddr52_c      : std_ulogic_vector(11 downto 0) := x"3e4";
569 
  constant csr_pmpaddr53_c      : std_ulogic_vector(11 downto 0) := x"3e5";
570 
  constant csr_pmpaddr54_c      : std_ulogic_vector(11 downto 0) := x"3e6";
571 
  constant csr_pmpaddr55_c      : std_ulogic_vector(11 downto 0) := x"3e7";
572 
  constant csr_pmpaddr56_c      : std_ulogic_vector(11 downto 0) := x"3e8";
573 
  constant csr_pmpaddr57_c      : std_ulogic_vector(11 downto 0) := x"3e9";
574 
  constant csr_pmpaddr58_c      : std_ulogic_vector(11 downto 0) := x"3ea";
575 
  constant csr_pmpaddr59_c      : std_ulogic_vector(11 downto 0) := x"3eb";
576 
  constant csr_pmpaddr60_c      : std_ulogic_vector(11 downto 0) := x"3ec";
577 
  constant csr_pmpaddr61_c      : std_ulogic_vector(11 downto 0) := x"3ed";
578 
  constant csr_pmpaddr62_c      : std_ulogic_vector(11 downto 0) := x"3ee";
579 
  constant csr_pmpaddr63_c      : std_ulogic_vector(11 downto 0) := x"3ef";
580 56 zero_gravi 
  -- machine counters/timers --
581 42 zero_gravi 
  constant csr_mcycle_c         : std_ulogic_vector(11 downto 0) := x"b00";
582 
  constant csr_minstret_c       : std_ulogic_vector(11 downto 0) := x"b02";
583 
  --
584 
  constant csr_mhpmcounter3_c   : std_ulogic_vector(11 downto 0) := x"b03";
585 
  constant csr_mhpmcounter4_c   : std_ulogic_vector(11 downto 0) := x"b04";
586 
  constant csr_mhpmcounter5_c   : std_ulogic_vector(11 downto 0) := x"b05";
587 
  constant csr_mhpmcounter6_c   : std_ulogic_vector(11 downto 0) := x"b06";
588 
  constant csr_mhpmcounter7_c   : std_ulogic_vector(11 downto 0) := x"b07";
589 
  constant csr_mhpmcounter8_c   : std_ulogic_vector(11 downto 0) := x"b08";
590 
  constant csr_mhpmcounter9_c   : std_ulogic_vector(11 downto 0) := x"b09";
591 
  constant csr_mhpmcounter10_c  : std_ulogic_vector(11 downto 0) := x"b0a";
592 
  constant csr_mhpmcounter11_c  : std_ulogic_vector(11 downto 0) := x"b0b";
593 
  constant csr_mhpmcounter12_c  : std_ulogic_vector(11 downto 0) := x"b0c";
594 
  constant csr_mhpmcounter13_c  : std_ulogic_vector(11 downto 0) := x"b0d";
595 
  constant csr_mhpmcounter14_c  : std_ulogic_vector(11 downto 0) := x"b0e";
596 
  constant csr_mhpmcounter15_c  : std_ulogic_vector(11 downto 0) := x"b0f";
597 
  constant csr_mhpmcounter16_c  : std_ulogic_vector(11 downto 0) := x"b10";
598 
  constant csr_mhpmcounter17_c  : std_ulogic_vector(11 downto 0) := x"b11";
599 
  constant csr_mhpmcounter18_c  : std_ulogic_vector(11 downto 0) := x"b12";
600 
  constant csr_mhpmcounter19_c  : std_ulogic_vector(11 downto 0) := x"b13";
601 
  constant csr_mhpmcounter20_c  : std_ulogic_vector(11 downto 0) := x"b14";
602 
  constant csr_mhpmcounter21_c  : std_ulogic_vector(11 downto 0) := x"b15";
603 
  constant csr_mhpmcounter22_c  : std_ulogic_vector(11 downto 0) := x"b16";
604 
  constant csr_mhpmcounter23_c  : std_ulogic_vector(11 downto 0) := x"b17";
605 
  constant csr_mhpmcounter24_c  : std_ulogic_vector(11 downto 0) := x"b18";
606 
  constant csr_mhpmcounter25_c  : std_ulogic_vector(11 downto 0) := x"b19";
607 
  constant csr_mhpmcounter26_c  : std_ulogic_vector(11 downto 0) := x"b1a";
608 
  constant csr_mhpmcounter27_c  : std_ulogic_vector(11 downto 0) := x"b1b";
609 
  constant csr_mhpmcounter28_c  : std_ulogic_vector(11 downto 0) := x"b1c";
610 
  constant csr_mhpmcounter29_c  : std_ulogic_vector(11 downto 0) := x"b1d";
611 
  constant csr_mhpmcounter30_c  : std_ulogic_vector(11 downto 0) := x"b1e";
612 
  constant csr_mhpmcounter31_c  : std_ulogic_vector(11 downto 0) := x"b1f";
613 
  --
614 
  constant csr_mcycleh_c        : std_ulogic_vector(11 downto 0) := x"b80";
615 
  constant csr_minstreth_c      : std_ulogic_vector(11 downto 0) := x"b82";
616 
  --
617 
  constant csr_mhpmcounter3h_c  : std_ulogic_vector(11 downto 0) := x"b83";
618 
  constant csr_mhpmcounter4h_c  : std_ulogic_vector(11 downto 0) := x"b84";
619 
  constant csr_mhpmcounter5h_c  : std_ulogic_vector(11 downto 0) := x"b85";
620 
  constant csr_mhpmcounter6h_c  : std_ulogic_vector(11 downto 0) := x"b86";
621 
  constant csr_mhpmcounter7h_c  : std_ulogic_vector(11 downto 0) := x"b87";
622 
  constant csr_mhpmcounter8h_c  : std_ulogic_vector(11 downto 0) := x"b88";
623 
  constant csr_mhpmcounter9h_c  : std_ulogic_vector(11 downto 0) := x"b89";
624 
  constant csr_mhpmcounter10h_c : std_ulogic_vector(11 downto 0) := x"b8a";
625 
  constant csr_mhpmcounter11h_c : std_ulogic_vector(11 downto 0) := x"b8b";
626 
  constant csr_mhpmcounter12h_c : std_ulogic_vector(11 downto 0) := x"b8c";
627 
  constant csr_mhpmcounter13h_c : std_ulogic_vector(11 downto 0) := x"b8d";
628 
  constant csr_mhpmcounter14h_c : std_ulogic_vector(11 downto 0) := x"b8e";
629 
  constant csr_mhpmcounter15h_c : std_ulogic_vector(11 downto 0) := x"b8f";
630 
  constant csr_mhpmcounter16h_c : std_ulogic_vector(11 downto 0) := x"b90";
631 
  constant csr_mhpmcounter17h_c : std_ulogic_vector(11 downto 0) := x"b91";
632 
  constant csr_mhpmcounter18h_c : std_ulogic_vector(11 downto 0) := x"b92";
633 
  constant csr_mhpmcounter19h_c : std_ulogic_vector(11 downto 0) := x"b93";
634 
  constant csr_mhpmcounter20h_c : std_ulogic_vector(11 downto 0) := x"b94";
635 
  constant csr_mhpmcounter21h_c : std_ulogic_vector(11 downto 0) := x"b95";
636 
  constant csr_mhpmcounter22h_c : std_ulogic_vector(11 downto 0) := x"b96";
637 
  constant csr_mhpmcounter23h_c : std_ulogic_vector(11 downto 0) := x"b97";
638 
  constant csr_mhpmcounter24h_c : std_ulogic_vector(11 downto 0) := x"b98";
639 
  constant csr_mhpmcounter25h_c : std_ulogic_vector(11 downto 0) := x"b99";
640 
  constant csr_mhpmcounter26h_c : std_ulogic_vector(11 downto 0) := x"b9a";
641 
  constant csr_mhpmcounter27h_c : std_ulogic_vector(11 downto 0) := x"b9b";
642 
  constant csr_mhpmcounter28h_c : std_ulogic_vector(11 downto 0) := x"b9c";
643 
  constant csr_mhpmcounter29h_c : std_ulogic_vector(11 downto 0) := x"b9d";
644 
  constant csr_mhpmcounter30h_c : std_ulogic_vector(11 downto 0) := x"b9e";
645 
  constant csr_mhpmcounter31h_c : std_ulogic_vector(11 downto 0) := x"b9f";
646 
 
647 56 zero_gravi 
  -- <<< standard read-only CSRs >>> --
648 
  -- user counters/timers --
649 42 zero_gravi 
  constant csr_cycle_c          : std_ulogic_vector(11 downto 0) := x"c00";
650 
  constant csr_time_c           : std_ulogic_vector(11 downto 0) := x"c01";
651 
  constant csr_instret_c        : std_ulogic_vector(11 downto 0) := x"c02";
652 29 zero_gravi 
  --
653 42 zero_gravi 
  constant csr_hpmcounter3_c    : std_ulogic_vector(11 downto 0) := x"c03";
654 
  constant csr_hpmcounter4_c    : std_ulogic_vector(11 downto 0) := x"c04";
655 
  constant csr_hpmcounter5_c    : std_ulogic_vector(11 downto 0) := x"c05";
656 
  constant csr_hpmcounter6_c    : std_ulogic_vector(11 downto 0) := x"c06";
657 
  constant csr_hpmcounter7_c    : std_ulogic_vector(11 downto 0) := x"c07";
658 
  constant csr_hpmcounter8_c    : std_ulogic_vector(11 downto 0) := x"c08";
659 
  constant csr_hpmcounter9_c    : std_ulogic_vector(11 downto 0) := x"c09";
660 
  constant csr_hpmcounter10_c   : std_ulogic_vector(11 downto 0) := x"c0a";
661 
  constant csr_hpmcounter11_c   : std_ulogic_vector(11 downto 0) := x"c0b";
662 
  constant csr_hpmcounter12_c   : std_ulogic_vector(11 downto 0) := x"c0c";
663 
  constant csr_hpmcounter13_c   : std_ulogic_vector(11 downto 0) := x"c0d";
664 
  constant csr_hpmcounter14_c   : std_ulogic_vector(11 downto 0) := x"c0e";
665 
  constant csr_hpmcounter15_c   : std_ulogic_vector(11 downto 0) := x"c0f";
666 
  constant csr_hpmcounter16_c   : std_ulogic_vector(11 downto 0) := x"c10";
667 
  constant csr_hpmcounter17_c   : std_ulogic_vector(11 downto 0) := x"c11";
668 
  constant csr_hpmcounter18_c   : std_ulogic_vector(11 downto 0) := x"c12";
669 
  constant csr_hpmcounter19_c   : std_ulogic_vector(11 downto 0) := x"c13";
670 
  constant csr_hpmcounter20_c   : std_ulogic_vector(11 downto 0) := x"c14";
671 
  constant csr_hpmcounter21_c   : std_ulogic_vector(11 downto 0) := x"c15";
672 
  constant csr_hpmcounter22_c   : std_ulogic_vector(11 downto 0) := x"c16";
673 
  constant csr_hpmcounter23_c   : std_ulogic_vector(11 downto 0) := x"c17";
674 
  constant csr_hpmcounter24_c   : std_ulogic_vector(11 downto 0) := x"c18";
675 
  constant csr_hpmcounter25_c   : std_ulogic_vector(11 downto 0) := x"c19";
676 
  constant csr_hpmcounter26_c   : std_ulogic_vector(11 downto 0) := x"c1a";
677 
  constant csr_hpmcounter27_c   : std_ulogic_vector(11 downto 0) := x"c1b";
678 
  constant csr_hpmcounter28_c   : std_ulogic_vector(11 downto 0) := x"c1c";
679 
  constant csr_hpmcounter29_c   : std_ulogic_vector(11 downto 0) := x"c1d";
680 
  constant csr_hpmcounter30_c   : std_ulogic_vector(11 downto 0) := x"c1e";
681 
  constant csr_hpmcounter31_c   : std_ulogic_vector(11 downto 0) := x"c1f";
682 29 zero_gravi 
  --
683 42 zero_gravi 
  constant csr_cycleh_c         : std_ulogic_vector(11 downto 0) := x"c80";
684 
  constant csr_timeh_c          : std_ulogic_vector(11 downto 0) := x"c81";
685 
  constant csr_instreth_c       : std_ulogic_vector(11 downto 0) := x"c82";
686 29 zero_gravi 
  --
687 42 zero_gravi 
  constant csr_hpmcounter3h_c   : std_ulogic_vector(11 downto 0) := x"c83";
688 
  constant csr_hpmcounter4h_c   : std_ulogic_vector(11 downto 0) := x"c84";
689 
  constant csr_hpmcounter5h_c   : std_ulogic_vector(11 downto 0) := x"c85";
690 
  constant csr_hpmcounter6h_c   : std_ulogic_vector(11 downto 0) := x"c86";
691 
  constant csr_hpmcounter7h_c   : std_ulogic_vector(11 downto 0) := x"c87";
692 
  constant csr_hpmcounter8h_c   : std_ulogic_vector(11 downto 0) := x"c88";
693 
  constant csr_hpmcounter9h_c   : std_ulogic_vector(11 downto 0) := x"c89";
694 
  constant csr_hpmcounter10h_c  : std_ulogic_vector(11 downto 0) := x"c8a";
695 
  constant csr_hpmcounter11h_c  : std_ulogic_vector(11 downto 0) := x"c8b";
696 
  constant csr_hpmcounter12h_c  : std_ulogic_vector(11 downto 0) := x"c8c";
697 
  constant csr_hpmcounter13h_c  : std_ulogic_vector(11 downto 0) := x"c8d";
698 
  constant csr_hpmcounter14h_c  : std_ulogic_vector(11 downto 0) := x"c8e";
699 
  constant csr_hpmcounter15h_c  : std_ulogic_vector(11 downto 0) := x"c8f";
700 
  constant csr_hpmcounter16h_c  : std_ulogic_vector(11 downto 0) := x"c90";
701 
  constant csr_hpmcounter17h_c  : std_ulogic_vector(11 downto 0) := x"c91";
702 
  constant csr_hpmcounter18h_c  : std_ulogic_vector(11 downto 0) := x"c92";
703 
  constant csr_hpmcounter19h_c  : std_ulogic_vector(11 downto 0) := x"c93";
704 
  constant csr_hpmcounter20h_c  : std_ulogic_vector(11 downto 0) := x"c94";
705 
  constant csr_hpmcounter21h_c  : std_ulogic_vector(11 downto 0) := x"c95";
706 
  constant csr_hpmcounter22h_c  : std_ulogic_vector(11 downto 0) := x"c96";
707 
  constant csr_hpmcounter23h_c  : std_ulogic_vector(11 downto 0) := x"c97";
708 
  constant csr_hpmcounter24h_c  : std_ulogic_vector(11 downto 0) := x"c98";
709 
  constant csr_hpmcounter25h_c  : std_ulogic_vector(11 downto 0) := x"c99";
710 
  constant csr_hpmcounter26h_c  : std_ulogic_vector(11 downto 0) := x"c9a";
711 
  constant csr_hpmcounter27h_c  : std_ulogic_vector(11 downto 0) := x"c9b";
712 
  constant csr_hpmcounter28h_c  : std_ulogic_vector(11 downto 0) := x"c9c";
713 
  constant csr_hpmcounter29h_c  : std_ulogic_vector(11 downto 0) := x"c9d";
714 
  constant csr_hpmcounter30h_c  : std_ulogic_vector(11 downto 0) := x"c9e";
715 
  constant csr_hpmcounter31h_c  : std_ulogic_vector(11 downto 0) := x"c9f";
716 56 zero_gravi 
  -- machine information registers --
717 42 zero_gravi 
  constant csr_mvendorid_c      : std_ulogic_vector(11 downto 0) := x"f11";
718 
  constant csr_marchid_c        : std_ulogic_vector(11 downto 0) := x"f12";
719 
  constant csr_mimpid_c         : std_ulogic_vector(11 downto 0) := x"f13";
720 
  constant csr_mhartid_c        : std_ulogic_vector(11 downto 0) := x"f14";
721 56 zero_gravi 
  -- <<< custom (NEORV32-specific) read-only CSRs >>> --
722 42 zero_gravi 
  constant csr_mzext_c          : std_ulogic_vector(11 downto 0) := x"fc0";
723 
 
724 44 zero_gravi 
  -- Co-Processor IDs -----------------------------------------------------------------------
725 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
726 49 zero_gravi 
  constant cp_sel_muldiv_c   : std_ulogic_vector(2 downto 0) := "000"; -- multiplication/division operations ('M' extension)
727 
  constant cp_sel_atomic_c   : std_ulogic_vector(2 downto 0) := "001"; -- atomic operations; success/failure evaluation ('A' extension)
728 
  constant cp_sel_bitmanip_c : std_ulogic_vector(2 downto 0) := "010"; -- bit manipulation ('B' extension)
729 
  constant cp_sel_csr_rd_c   : std_ulogic_vector(2 downto 0) := "011"; -- CSR read access ('Zicsr' extension)
730 53 zero_gravi 
  constant cp_sel_fpu_c      : std_ulogic_vector(2 downto 0) := "100"; -- loating-point unit ('Zfinx' extension)
731 
--constant cp_sel_crypto_c   : std_ulogic_vector(2 downto 0) := "101"; -- crypto operations ('K' extension)
732 52 zero_gravi 
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "110"; -- reserved
733 
--constant cp_sel_reserved_c : std_ulogic_vector(2 downto 0) := "111"; -- reserved
734 2 zero_gravi 
 
735 
  -- ALU Function Codes ---------------------------------------------------------------------
736 
  -- -------------------------------------------------------------------------------------------
737 39 zero_gravi 
  -- arithmetic core --
738 
  constant alu_arith_cmd_addsub_c : std_ulogic := '0'; -- r.arith <= A +/- B
739 
  constant alu_arith_cmd_slt_c    : std_ulogic := '1'; -- r.arith <= A < B
740 
  -- logic core --
741 
  constant alu_logic_cmd_movb_c   : std_ulogic_vector(1 downto 0) := "00"; -- r.logic <= B
742 
  constant alu_logic_cmd_xor_c    : std_ulogic_vector(1 downto 0) := "01"; -- r.logic <= A xor B
743 
  constant alu_logic_cmd_or_c     : std_ulogic_vector(1 downto 0) := "10"; -- r.logic <= A or B
744 
  constant alu_logic_cmd_and_c    : std_ulogic_vector(1 downto 0) := "11"; -- r.logic <= A and B
745 
  -- function select (actual alu result) --
746 
  constant alu_func_cmd_arith_c   : std_ulogic_vector(1 downto 0) := "00"; -- r <= r.arith
747 
  constant alu_func_cmd_logic_c   : std_ulogic_vector(1 downto 0) := "01"; -- r <= r.logic
748 
  constant alu_func_cmd_shift_c   : std_ulogic_vector(1 downto 0) := "10"; -- r <= A <</>> B (iterative)
749 
  constant alu_func_cmd_copro_c   : std_ulogic_vector(1 downto 0) := "11"; -- r <= CP result (iterative)
750 2 zero_gravi 
 
751 12 zero_gravi 
  -- Trap ID Codes --------------------------------------------------------------------------
752 
  -- -------------------------------------------------------------------------------------------
753 48 zero_gravi 
  -- RISC-V compliant sync. exceptions --
754 
  constant trap_ima_c    : std_ulogic_vector(5 downto 0) := "0" & "00000"; -- 0.0:  instruction misaligned
755 
  constant trap_iba_c    : std_ulogic_vector(5 downto 0) := "0" & "00001"; -- 0.1:  instruction access fault
756 
  constant trap_iil_c    : std_ulogic_vector(5 downto 0) := "0" & "00010"; -- 0.2:  illegal instruction
757 
  constant trap_brk_c    : std_ulogic_vector(5 downto 0) := "0" & "00011"; -- 0.3:  breakpoint
758 
  constant trap_lma_c    : std_ulogic_vector(5 downto 0) := "0" & "00100"; -- 0.4:  load address misaligned
759 
  constant trap_lbe_c    : std_ulogic_vector(5 downto 0) := "0" & "00101"; -- 0.5:  load access fault
760 
  constant trap_sma_c    : std_ulogic_vector(5 downto 0) := "0" & "00110"; -- 0.6:  store address misaligned
761 
  constant trap_sbe_c    : std_ulogic_vector(5 downto 0) := "0" & "00111"; -- 0.7:  store access fault
762 
  constant trap_uenv_c   : std_ulogic_vector(5 downto 0) := "0" & "01000"; -- 0.8:  environment call from u-mode
763 
  constant trap_menv_c   : std_ulogic_vector(5 downto 0) := "0" & "01011"; -- 0.11: environment call from m-mode
764 
  -- RISC-V compliant interrupts (async. exceptions) --
765 
  constant trap_msi_c    : std_ulogic_vector(5 downto 0) := "1" & "00011"; -- 1.3:  machine software interrupt
766 
  constant trap_mti_c    : std_ulogic_vector(5 downto 0) := "1" & "00111"; -- 1.7:  machine timer interrupt
767 
  constant trap_mei_c    : std_ulogic_vector(5 downto 0) := "1" & "01011"; -- 1.11: machine external interrupt
768 
  -- NEORV32-specific (custom) interrupts (async. exceptions) --
769 
  constant trap_firq0_c  : std_ulogic_vector(5 downto 0) := "1" & "10000"; -- 1.16: fast interrupt 0
770 
  constant trap_firq1_c  : std_ulogic_vector(5 downto 0) := "1" & "10001"; -- 1.17: fast interrupt 1
771 
  constant trap_firq2_c  : std_ulogic_vector(5 downto 0) := "1" & "10010"; -- 1.18: fast interrupt 2
772 
  constant trap_firq3_c  : std_ulogic_vector(5 downto 0) := "1" & "10011"; -- 1.19: fast interrupt 3
773 
  constant trap_firq4_c  : std_ulogic_vector(5 downto 0) := "1" & "10100"; -- 1.20: fast interrupt 4
774 
  constant trap_firq5_c  : std_ulogic_vector(5 downto 0) := "1" & "10101"; -- 1.21: fast interrupt 5
775 
  constant trap_firq6_c  : std_ulogic_vector(5 downto 0) := "1" & "10110"; -- 1.22: fast interrupt 6
776 
  constant trap_firq7_c  : std_ulogic_vector(5 downto 0) := "1" & "10111"; -- 1.23: fast interrupt 7
777 
  constant trap_firq8_c  : std_ulogic_vector(5 downto 0) := "1" & "11000"; -- 1.24: fast interrupt 8
778 
  constant trap_firq9_c  : std_ulogic_vector(5 downto 0) := "1" & "11001"; -- 1.25: fast interrupt 9
779 
  constant trap_firq10_c : std_ulogic_vector(5 downto 0) := "1" & "11010"; -- 1.26: fast interrupt 10
780 
  constant trap_firq11_c : std_ulogic_vector(5 downto 0) := "1" & "11011"; -- 1.27: fast interrupt 11
781 
  constant trap_firq12_c : std_ulogic_vector(5 downto 0) := "1" & "11100"; -- 1.28: fast interrupt 12
782 
  constant trap_firq13_c : std_ulogic_vector(5 downto 0) := "1" & "11101"; -- 1.29: fast interrupt 13
783 
  constant trap_firq14_c : std_ulogic_vector(5 downto 0) := "1" & "11110"; -- 1.30: fast interrupt 14
784 
  constant trap_firq15_c : std_ulogic_vector(5 downto 0) := "1" & "11111"; -- 1.31: fast interrupt 15
785 12 zero_gravi 
 
786 2 zero_gravi 
  -- CPU Control Exception System -----------------------------------------------------------
787 
  -- -------------------------------------------------------------------------------------------
788 
  -- exception source bits --
789 47 zero_gravi 
  constant exception_iaccess_c   : natural :=  0; -- instrution access fault
790 
  constant exception_iillegal_c  : natural :=  1; -- illegal instrution
791 
  constant exception_ialign_c    : natural :=  2; -- instrution address misaligned
792 
  constant exception_m_envcall_c : natural :=  3; -- ENV call from m-mode
793 
  constant exception_u_envcall_c : natural :=  4; -- ENV call from u-mode
794 
  constant exception_break_c     : natural :=  5; -- breakpoint
795 
  constant exception_salign_c    : natural :=  6; -- store address misaligned
796 
  constant exception_lalign_c    : natural :=  7; -- load address misaligned
797 
  constant exception_saccess_c   : natural :=  8; -- store access fault
798 
  constant exception_laccess_c   : natural :=  9; -- load access fault
799 14 zero_gravi 
  --
800 40 zero_gravi 
  constant exception_width_c     : natural := 10; -- length of this list in bits
801 2 zero_gravi 
  -- interrupt source bits --
802 47 zero_gravi 
  constant interrupt_msw_irq_c   : natural :=  0; -- machine software interrupt
803 
  constant interrupt_mtime_irq_c : natural :=  1; -- machine timer interrupt
804 
  constant interrupt_mext_irq_c  : natural :=  2; -- machine external interrupt
805 
  constant interrupt_firq_0_c    : natural :=  3; -- fast interrupt channel 0
806 
  constant interrupt_firq_1_c    : natural :=  4; -- fast interrupt channel 1
807 
  constant interrupt_firq_2_c    : natural :=  5; -- fast interrupt channel 2
808 
  constant interrupt_firq_3_c    : natural :=  6; -- fast interrupt channel 3
809 
  constant interrupt_firq_4_c    : natural :=  7; -- fast interrupt channel 4
810 
  constant interrupt_firq_5_c    : natural :=  8; -- fast interrupt channel 5
811 
  constant interrupt_firq_6_c    : natural :=  9; -- fast interrupt channel 6
812 
  constant interrupt_firq_7_c    : natural := 10; -- fast interrupt channel 7
813 48 zero_gravi 
  constant interrupt_firq_8_c    : natural := 11; -- fast interrupt channel 8
814 
  constant interrupt_firq_9_c    : natural := 12; -- fast interrupt channel 9
815 
  constant interrupt_firq_10_c   : natural := 13; -- fast interrupt channel 10
816 
  constant interrupt_firq_11_c   : natural := 14; -- fast interrupt channel 11
817 
  constant interrupt_firq_12_c   : natural := 15; -- fast interrupt channel 12
818 
  constant interrupt_firq_13_c   : natural := 16; -- fast interrupt channel 13
819 
  constant interrupt_firq_14_c   : natural := 17; -- fast interrupt channel 14
820 
  constant interrupt_firq_15_c   : natural := 18; -- fast interrupt channel 15
821 14 zero_gravi 
  --
822 48 zero_gravi 
  constant interrupt_width_c     : natural := 19; -- length of this list in bits
823 2 zero_gravi 
 
824 15 zero_gravi 
  -- CPU Privilege Modes --------------------------------------------------------------------
825 
  -- -------------------------------------------------------------------------------------------
826 29 zero_gravi 
  constant priv_mode_m_c : std_ulogic_vector(1 downto 0) := "11"; -- machine mode
827 
  constant priv_mode_u_c : std_ulogic_vector(1 downto 0) := "00"; -- user mode
828 15 zero_gravi 
 
829 42 zero_gravi 
  -- HPM Event System -----------------------------------------------------------------------
830 
  -- -------------------------------------------------------------------------------------------
831 
  constant hpmcnt_event_cy_c      : natural := 0;  -- Active cycle
832 56 zero_gravi 
  constant hpmcnt_event_never_c   : natural := 1;  -- Unused / never (actually, this would be used for TIME)
833 42 zero_gravi 
  constant hpmcnt_event_ir_c      : natural := 2;  -- Retired instruction
834 
  constant hpmcnt_event_cir_c     : natural := 3;  -- Retired compressed instruction
835 
  constant hpmcnt_event_wait_if_c : natural := 4;  -- Instruction fetch memory wait cycle
836 
  constant hpmcnt_event_wait_ii_c : natural := 5;  -- Instruction issue wait cycle
837 45 zero_gravi 
  constant hpmcnt_event_wait_mc_c : natural := 6;  -- Multi-cycle ALU-operation wait cycle
838 
  constant hpmcnt_event_load_c    : natural := 7;  -- Load operation
839 
  constant hpmcnt_event_store_c   : natural := 8;  -- Store operation
840 
  constant hpmcnt_event_wait_ls_c : natural := 9;  -- Load/store memory wait cycle
841 
  constant hpmcnt_event_jump_c    : natural := 10; -- Unconditional jump
842 
  constant hpmcnt_event_branch_c  : natural := 11; -- Conditional branch (taken or not taken)
843 
  constant hpmcnt_event_tbranch_c : natural := 12; -- Conditional taken branch
844 
  constant hpmcnt_event_trap_c    : natural := 13; -- Entered trap
845 
  constant hpmcnt_event_illegal_c : natural := 14; -- Illegal instruction exception
846 42 zero_gravi 
  --
847 45 zero_gravi 
  constant hpmcnt_event_size_c    : natural := 15; -- length of this list
848 42 zero_gravi 
 
849 39 zero_gravi 
  -- Clock Generator ------------------------------------------------------------------------
850 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
851 
  constant clk_div2_c    : natural := 0;
852 
  constant clk_div4_c    : natural := 1;
853 
  constant clk_div8_c    : natural := 2;
854 
  constant clk_div64_c   : natural := 3;
855 
  constant clk_div128_c  : natural := 4;
856 
  constant clk_div1024_c : natural := 5;
857 
  constant clk_div2048_c : natural := 6;
858 
  constant clk_div4096_c : natural := 7;
859 
 
860 
  -- Component: NEORV32 Processor Top Entity ------------------------------------------------
861 
  -- -------------------------------------------------------------------------------------------
862 
  component neorv32_top
863 
    generic (
864 
      -- General --
865 12 zero_gravi 
      CLOCK_FREQUENCY              : natural := 0;      -- clock frequency of clk_i in Hz
866 44 zero_gravi 
      BOOTLOADER_EN                : boolean := true;   -- implement processor-internal bootloader?
867 12 zero_gravi 
      USER_CODE                    : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
868 49 zero_gravi 
      HW_THREAD_ID                 : natural := 0;      -- hardware thread id (32-bit)
869 2 zero_gravi 
      -- RISC-V CPU Extensions --
870 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false;  -- implement atomic extension?
871 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false;  -- implement bit manipulation extensions?
872 18 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false;  -- implement compressed extension?
873 8 zero_gravi 
      CPU_EXTENSION_RISCV_E        : boolean := false;  -- implement embedded RF extension?
874 18 zero_gravi 
      CPU_EXTENSION_RISCV_M        : boolean := false;  -- implement muld/div extension?
875 
      CPU_EXTENSION_RISCV_U        : boolean := false;  -- implement user mode extension?
876 56 zero_gravi 
      CPU_EXTENSION_RISCV_Zfinx    : boolean := false;  -- implement 32-bit floating-point extension (using INT reg!)
877 8 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;   -- implement CSR system?
878 39 zero_gravi 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false;  -- implement instruction stream sync.?
879 19 zero_gravi 
      -- Extension Options --
880 34 zero_gravi 
      FAST_MUL_EN                  : boolean := false;  -- use DSPs for M extension's multiplier
881 
      FAST_SHIFT_EN                : boolean := false;  -- use barrel shifter for shift operations
882 56 zero_gravi 
      TINY_SHIFT_EN                : boolean := false;  -- use tiny (single-bit) shifter for shift operations
883 
      CPU_CNT_WIDTH                : natural := 64;     -- total width of CPU cycle and instret counters (0..64)
884 15 zero_gravi 
      -- Physical Memory Protection (PMP) --
885 42 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0;      -- number of regions (0..64)
886 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
887 
      -- Hardware Performance Monitors (HPM) --
888 47 zero_gravi 
      HPM_NUM_CNTS                 : natural := 0;      -- number of implemented HPM counters (0..29)
889 56 zero_gravi 
      HPM_CNT_WIDTH                : natural := 40;     -- total size of HPM counters (1..64)
890 23 zero_gravi 
      -- Internal Instruction memory --
891 44 zero_gravi 
      MEM_INT_IMEM_EN              : boolean := true;   -- implement processor-internal instruction memory
892 8 zero_gravi 
      MEM_INT_IMEM_SIZE            : natural := 16*1024; -- size of processor-internal instruction memory in bytes
893 34 zero_gravi 
      MEM_INT_IMEM_ROM             : boolean := false;  -- implement processor-internal instruction memory as ROM
894 23 zero_gravi 
      -- Internal Data memory --
895 44 zero_gravi 
      MEM_INT_DMEM_EN              : boolean := true;   -- implement processor-internal data memory
896 8 zero_gravi 
      MEM_INT_DMEM_SIZE            : natural := 8*1024; -- size of processor-internal data memory in bytes
897 41 zero_gravi 
      -- Internal Cache memory --
898 44 zero_gravi 
      ICACHE_EN                    : boolean := false;  -- implement instruction cache
899 41 zero_gravi 
      ICACHE_NUM_BLOCKS            : natural := 4;      -- i-cache: number of blocks (min 1), has to be a power of 2
900 
      ICACHE_BLOCK_SIZE            : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
901 45 zero_gravi 
      ICACHE_ASSOCIATIVITY         : natural := 1;      -- i-cache: associativity / number of sets (1=direct_mapped), has to be a power of 2
902 23 zero_gravi 
      -- External memory interface --
903 44 zero_gravi 
      MEM_EXT_EN                   : boolean := false;  -- implement external memory bus interface?
904 2 zero_gravi 
      -- Processor peripherals --
905 44 zero_gravi 
      IO_GPIO_EN                   : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
906 
      IO_MTIME_EN                  : boolean := true;   -- implement machine system timer (MTIME)?
907 50 zero_gravi 
      IO_UART0_EN                  : boolean := true;   -- implement primary universal asynchronous receiver/transmitter (UART0)?
908 
      IO_UART1_EN                  : boolean := true;   -- implement secondary universal asynchronous receiver/transmitter (UART1)?
909 44 zero_gravi 
      IO_SPI_EN                    : boolean := true;   -- implement serial peripheral interface (SPI)?
910 
      IO_TWI_EN                    : boolean := true;   -- implement two-wire interface (TWI)?
911 
      IO_PWM_EN                    : boolean := true;   -- implement pulse-width modulation unit (PWM)?
912 
      IO_WDT_EN                    : boolean := true;   -- implement watch dog timer (WDT)?
913 
      IO_TRNG_EN                   : boolean := false;  -- implement true random number generator (TRNG)?
914 47 zero_gravi 
      IO_CFS_EN                    : boolean := false;  -- implement custom functions subsystem (CFS)?
915 56 zero_gravi 
      IO_CFS_CONFIG                : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom CFS configuration generic
916 52 zero_gravi 
      IO_CFS_IN_SIZE               : positive := 32;    -- size of CFS input conduit in bits
917 
      IO_CFS_OUT_SIZE              : positive := 32;    -- size of CFS output conduit in bits
918 
      IO_NCO_EN                    : boolean := true;   -- implement numerically-controlled oscillator (NCO)?
919 
      IO_NEOLED_EN                 : boolean := true    -- implement NeoPixel-compatible smart LED interface (NEOLED)?
920 2 zero_gravi 
    );
921 
    port (
922 
      -- Global control --
923 34 zero_gravi 
      clk_i       : in  std_ulogic := '0'; -- global clock, rising edge
924 
      rstn_i      : in  std_ulogic := '0'; -- global reset, low-active, async
925 49 zero_gravi 
      -- Wishbone bus interface (available if MEM_EXT_EN = true) --
926 53 zero_gravi 
      wb_tag_o    : out std_ulogic_vector(03 downto 0); -- request tag
927 34 zero_gravi 
      wb_adr_o    : out std_ulogic_vector(31 downto 0); -- address
928 
      wb_dat_i    : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- read data
929 
      wb_dat_o    : out std_ulogic_vector(31 downto 0); -- write data
930 
      wb_we_o     : out std_ulogic; -- read/write
931 
      wb_sel_o    : out std_ulogic_vector(03 downto 0); -- byte enable
932 
      wb_stb_o    : out std_ulogic; -- strobe
933 
      wb_cyc_o    : out std_ulogic; -- valid cycle
934 53 zero_gravi 
      wb_tag_i    : in  std_ulogic; -- response tag
935 34 zero_gravi 
      wb_ack_i    : in  std_ulogic := '0'; -- transfer acknowledge
936 
      wb_err_i    : in  std_ulogic := '0'; -- transfer error
937 44 zero_gravi 
      -- Advanced memory control signals (available if MEM_EXT_EN = true) --
938 34 zero_gravi 
      fence_o     : out std_ulogic; -- indicates an executed FENCE operation
939 
      fencei_o    : out std_ulogic; -- indicates an executed FENCEI operation
940 49 zero_gravi 
      -- GPIO (available if IO_GPIO_EN = true) --
941 34 zero_gravi 
      gpio_o      : out std_ulogic_vector(31 downto 0); -- parallel output
942 
      gpio_i      : in  std_ulogic_vector(31 downto 0) := (others => '0'); -- parallel input
943 50 zero_gravi 
      -- primary UART0 (available if IO_UART0_EN = true) --
944 
      uart0_txd_o : out std_ulogic; -- UART0 send data
945 
      uart0_rxd_i : in  std_ulogic := '0'; -- UART0 receive data
946 51 zero_gravi 
      uart0_rts_o : out std_ulogic; -- hw flow control: UART0.RX ready to receive ("RTR"), low-active, optional
947 
      uart0_cts_i : in  std_ulogic := '0'; -- hw flow control: UART0.TX allowed to transmit, low-active, optional
948 50 zero_gravi 
      -- secondary UART1 (available if IO_UART1_EN = true) --
949 
      uart1_txd_o : out std_ulogic; -- UART1 send data
950 
      uart1_rxd_i : in  std_ulogic := '0'; -- UART1 receive data
951 51 zero_gravi 
      uart1_rts_o : out std_ulogic; -- hw flow control: UART1.RX ready to receive ("RTR"), low-active, optional
952 
      uart1_cts_i : in  std_ulogic := '0'; -- hw flow control: UART1.TX allowed to transmit, low-active, optional
953 49 zero_gravi 
      -- SPI (available if IO_SPI_EN = true) --
954 34 zero_gravi 
      spi_sck_o   : out std_ulogic; -- SPI serial clock
955 
      spi_sdo_o   : out std_ulogic; -- controller data out, peripheral data in
956 
      spi_sdi_i   : in  std_ulogic := '0'; -- controller data in, peripheral data out
957 
      spi_csn_o   : out std_ulogic_vector(07 downto 0); -- SPI CS
958 49 zero_gravi 
      -- TWI (available if IO_TWI_EN = true) --
959 35 zero_gravi 
      twi_sda_io  : inout std_logic; -- twi serial data line
960 
      twi_scl_io  : inout std_logic; -- twi serial clock line
961 49 zero_gravi 
      -- PWM (available if IO_PWM_EN = true) --
962 40 zero_gravi 
      pwm_o       : out std_ulogic_vector(03 downto 0); -- pwm channels
963 47 zero_gravi 
      -- Custom Functions Subsystem IO --
964 52 zero_gravi 
      cfs_in_i    : in  std_ulogic_vector(IO_CFS_IN_SIZE-1  downto 0); -- custom CFS inputs conduit
965 
      cfs_out_o   : out std_ulogic_vector(IO_CFS_OUT_SIZE-1 downto 0); -- custom CFS outputs conduit
966 49 zero_gravi 
      -- NCO output (available if IO_NCO_EN = true) --
967 
      nco_o       : out std_ulogic_vector(02 downto 0); -- numerically-controlled oscillator channels
968 52 zero_gravi 
      -- NeoPixel-compatible smart LED interface (available if IO_NEOLED_EN = true) --
969 
      neoled_o    : out std_ulogic; -- async serial data line
970 44 zero_gravi 
      -- system time input from external MTIME (available if IO_MTIME_EN = false) --
971 40 zero_gravi 
      mtime_i     : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
972 2 zero_gravi 
      -- Interrupts --
973 50 zero_gravi 
      soc_firq_i  : in  std_ulogic_vector(5 downto 0) := (others => '0'); -- fast interrupt channels
974 44 zero_gravi 
      mtime_irq_i : in  std_ulogic := '0'; -- machine timer interrupt, available if IO_MTIME_EN = false
975 34 zero_gravi 
      msw_irq_i   : in  std_ulogic := '0'; -- machine software interrupt
976 
      mext_irq_i  : in  std_ulogic := '0'  -- machine external interrupt
977 2 zero_gravi 
    );
978 
  end component;
979 
 
980 4 zero_gravi 
  -- Component: CPU Top Entity --------------------------------------------------------------
981 
  -- -------------------------------------------------------------------------------------------
982 
  component neorv32_cpu
983 
    generic (
984 
      -- General --
985 49 zero_gravi 
      HW_THREAD_ID                 : natural := 0;     -- hardware thread id (32-bit)
986 
      CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0) := x"00000000"; -- cpu boot address
987 41 zero_gravi 
      BUS_TIMEOUT                  : natural := 63;    -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
988 4 zero_gravi 
      -- RISC-V CPU Extensions --
989 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
990 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false; -- implement bit manipulation extensions?
991 12 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
992 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
993 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
994 15 zero_gravi 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
995 53 zero_gravi 
      CPU_EXTENSION_RISCV_Zfinx    : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
996 12 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
997 49 zero_gravi 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
998 19 zero_gravi 
      -- Extension Options --
999 
      FAST_MUL_EN                  : boolean := false; -- use DSPs for M extension's multiplier
1000 34 zero_gravi 
      FAST_SHIFT_EN                : boolean := false; -- use barrel shifter for shift operations
1001 56 zero_gravi 
      TINY_SHIFT_EN                : boolean := false; -- use tiny (single-bit) shifter for shift operations
1002 
      CPU_CNT_WIDTH                : natural := 64;    -- total width of CPU cycle and instret counters (0..64)
1003 15 zero_gravi 
      -- Physical Memory Protection (PMP) --
1004 52 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0;     -- number of regions (0..64)
1005 42 zero_gravi 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
1006 
      -- Hardware Performance Monitors (HPM) --
1007 56 zero_gravi 
      HPM_NUM_CNTS                 : natural := 0;     -- number of implemented HPM counters (0..29)
1008 
      HPM_CNT_WIDTH                : natural := 40     -- total size of HPM counters (1..64)
1009 4 zero_gravi 
    );
1010 
    port (
1011 
      -- global control --
1012 14 zero_gravi 
      clk_i          : in  std_ulogic := '0'; -- global clock, rising edge
1013 
      rstn_i         : in  std_ulogic := '0'; -- global reset, low-active, async
1014 47 zero_gravi 
      sleep_o        : out std_ulogic; -- cpu is in sleep mode when set
1015 12 zero_gravi 
      -- instruction bus interface --
1016 
      i_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1017 14 zero_gravi 
      i_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
1018 12 zero_gravi 
      i_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1019 
      i_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1020 
      i_bus_we_o     : out std_ulogic; -- write enable
1021 
      i_bus_re_o     : out std_ulogic; -- read enable
1022 53 zero_gravi 
      i_bus_cancel_o : out std_ulogic := '0'; -- cancel current bus transaction
1023 14 zero_gravi 
      i_bus_ack_i    : in  std_ulogic := '0'; -- bus transfer acknowledge
1024 
      i_bus_err_i    : in  std_ulogic := '0'; -- bus transfer error
1025 12 zero_gravi 
      i_bus_fence_o  : out std_ulogic; -- executed FENCEI operation
1026 35 zero_gravi 
      i_bus_priv_o   : out std_ulogic_vector(1 downto 0); -- privilege level
1027 12 zero_gravi 
      -- data bus interface --
1028 
      d_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1029 14 zero_gravi 
      d_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0) := (others => '0'); -- bus read data
1030 12 zero_gravi 
      d_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1031 
      d_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1032 
      d_bus_we_o     : out std_ulogic; -- write enable
1033 
      d_bus_re_o     : out std_ulogic; -- read enable
1034 
      d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
1035 14 zero_gravi 
      d_bus_ack_i    : in  std_ulogic := '0'; -- bus transfer acknowledge
1036 
      d_bus_err_i    : in  std_ulogic := '0'; -- bus transfer error
1037 12 zero_gravi 
      d_bus_fence_o  : out std_ulogic; -- executed FENCE operation
1038 35 zero_gravi 
      d_bus_priv_o   : out std_ulogic_vector(1 downto 0); -- privilege level
1039 53 zero_gravi 
      d_bus_excl_o   : out std_ulogic; -- exclusive access
1040 
      d_bus_excl_i   : in  std_ulogic; -- state of exclusiv access (set if success)
1041 11 zero_gravi 
      -- system time input from MTIME --
1042 14 zero_gravi 
      time_i         : in  std_ulogic_vector(63 downto 0) := (others => '0'); -- current system time
1043 
      -- interrupts (risc-v compliant) --
1044 
      msw_irq_i      : in  std_ulogic := '0'; -- machine software interrupt
1045 
      mext_irq_i     : in  std_ulogic := '0'; -- machine external interrupt
1046 
      mtime_irq_i    : in  std_ulogic := '0'; -- machine timer interrupt
1047 
      -- fast interrupts (custom) --
1048 48 zero_gravi 
      firq_i         : in  std_ulogic_vector(15 downto 0) := (others => '0');
1049 
      firq_ack_o     : out std_ulogic_vector(15 downto 0)
1050 4 zero_gravi 
    );
1051 
  end component;
1052 
 
1053 2 zero_gravi 
  -- Component: CPU Control -----------------------------------------------------------------
1054 
  -- -------------------------------------------------------------------------------------------
1055 
  component neorv32_cpu_control
1056 
    generic (
1057 
      -- General --
1058 49 zero_gravi 
      HW_THREAD_ID                 : natural := 0;     -- hardware thread id (32-bit)
1059 12 zero_gravi 
      CPU_BOOT_ADDR                : std_ulogic_vector(31 downto 0):= x"00000000"; -- cpu boot address
1060 2 zero_gravi 
      -- RISC-V CPU Extensions --
1061 39 zero_gravi 
      CPU_EXTENSION_RISCV_A        : boolean := false; -- implement atomic extension?
1062 44 zero_gravi 
      CPU_EXTENSION_RISCV_B        : boolean := false; -- implement bit manipulation extensions?
1063 12 zero_gravi 
      CPU_EXTENSION_RISCV_C        : boolean := false; -- implement compressed extension?
1064 
      CPU_EXTENSION_RISCV_E        : boolean := false; -- implement embedded RF extension?
1065 
      CPU_EXTENSION_RISCV_M        : boolean := false; -- implement muld/div extension?
1066 15 zero_gravi 
      CPU_EXTENSION_RISCV_U        : boolean := false; -- implement user mode extension?
1067 53 zero_gravi 
      CPU_EXTENSION_RISCV_Zfinx    : boolean := false; -- implement 32-bit floating-point extension (using INT reg!)
1068 12 zero_gravi 
      CPU_EXTENSION_RISCV_Zicsr    : boolean := true;  -- implement CSR system?
1069 49 zero_gravi 
      CPU_EXTENSION_RISCV_Zifencei : boolean := false; -- implement instruction stream sync.?
1070 56 zero_gravi 
      -- Extension Options --
1071 
      CPU_CNT_WIDTH                : natural := 64; -- total width of CPU cycle and instret counters (0..64)
1072 15 zero_gravi 
      -- Physical memory protection (PMP) --
1073 52 zero_gravi 
      PMP_NUM_REGIONS              : natural := 0;     -- number of regions (0..64)
1074 42 zero_gravi 
      PMP_MIN_GRANULARITY          : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
1075 
      -- Hardware Performance Monitors (HPM) --
1076 56 zero_gravi 
      HPM_NUM_CNTS                 : natural := 0;     -- number of implemented HPM counters (0..29)
1077 
      HPM_CNT_WIDTH                : natural := 40     -- total size of HPM counters (1..64)
1078 2 zero_gravi 
    );
1079 
    port (
1080 
      -- global control --
1081 
      clk_i         : in  std_ulogic; -- global clock, rising edge
1082 
      rstn_i        : in  std_ulogic; -- global reset, low-active, async
1083 
      ctrl_o        : out std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1084 
      -- status input --
1085 
      alu_wait_i    : in  std_ulogic; -- wait for ALU
1086 12 zero_gravi 
      bus_i_wait_i  : in  std_ulogic; -- wait for bus
1087 
      bus_d_wait_i  : in  std_ulogic; -- wait for bus
1088 2 zero_gravi 
      -- data input --
1089 
      instr_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- instruction
1090 
      cmp_i         : in  std_ulogic_vector(1 downto 0); -- comparator status
1091 36 zero_gravi 
      alu_add_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU address result
1092 52 zero_gravi 
      rs1_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1093 2 zero_gravi 
      -- data output --
1094 
      imm_o         : out std_ulogic_vector(data_width_c-1 downto 0); -- immediate
1095 6 zero_gravi 
      fetch_pc_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
1096 
      curr_pc_o     : out std_ulogic_vector(data_width_c-1 downto 0); -- current PC (corresponding to current instruction)
1097 2 zero_gravi 
      csr_rdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- CSR read data
1098 52 zero_gravi 
      -- FPU interface --
1099 
      fpu_rm_o      : out std_ulogic_vector(02 downto 0); -- rounding mode
1100 
      fpu_flags_i   : in  std_ulogic_vector(04 downto 0); -- exception flags
1101 14 zero_gravi 
      -- interrupts (risc-v compliant) --
1102 
      msw_irq_i     : in  std_ulogic; -- machine software interrupt
1103 
      mext_irq_i    : in  std_ulogic; -- machine external interrupt
1104 2 zero_gravi 
      mtime_irq_i   : in  std_ulogic; -- machine timer interrupt
1105 14 zero_gravi 
      -- fast interrupts (custom) --
1106 48 zero_gravi 
      firq_i        : in  std_ulogic_vector(15 downto 0);
1107 
      firq_ack_o    : out std_ulogic_vector(15 downto 0);
1108 11 zero_gravi 
      -- system time input from MTIME --
1109 
      time_i        : in  std_ulogic_vector(63 downto 0); -- current system time
1110 15 zero_gravi 
      -- physical memory protection --
1111 
      pmp_addr_o    : out pmp_addr_if_t; -- addresses
1112 
      pmp_ctrl_o    : out pmp_ctrl_if_t; -- configs
1113 2 zero_gravi 
      -- bus access exceptions --
1114 
      mar_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- memory address register
1115 
      ma_instr_i    : in  std_ulogic; -- misaligned instruction address
1116 
      ma_load_i     : in  std_ulogic; -- misaligned load data address
1117 
      ma_store_i    : in  std_ulogic; -- misaligned store data address
1118 
      be_instr_i    : in  std_ulogic; -- bus error on instruction access
1119 
      be_load_i     : in  std_ulogic; -- bus error on load data access
1120 12 zero_gravi 
      be_store_i    : in  std_ulogic  -- bus error on store data access
1121 2 zero_gravi 
    );
1122 
  end component;
1123 
 
1124 
  -- Component: CPU Register File -----------------------------------------------------------
1125 
  -- -------------------------------------------------------------------------------------------
1126 
  component neorv32_cpu_regfile
1127 
    generic (
1128 
      CPU_EXTENSION_RISCV_E : boolean := false -- implement embedded RF extension?
1129 
    );
1130 
    port (
1131 
      -- global control --
1132 
      clk_i  : in  std_ulogic; -- global clock, rising edge
1133 
      ctrl_i : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1134 
      -- data input --
1135 
      mem_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- memory read data
1136 
      alu_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
1137 
      -- data output --
1138 
      rs1_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 1
1139 47 zero_gravi 
      rs2_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- operand 2
1140 
      cmp_o  : out std_ulogic_vector(1 downto 0) -- comparator status
1141 2 zero_gravi 
    );
1142 
  end component;
1143 
 
1144 
  -- Component: CPU ALU ---------------------------------------------------------------------
1145 
  -- -------------------------------------------------------------------------------------------
1146 
  component neorv32_cpu_alu
1147 11 zero_gravi 
    generic (
1148 56 zero_gravi 
      CPU_EXTENSION_RISCV_M : boolean := true;  -- implement muld/div extension?
1149 
      FAST_SHIFT_EN         : boolean := false; -- use barrel shifter for shift operations
1150 
      TINY_SHIFT_EN         : boolean := false  -- use tiny (single-bit) shifter for shift operations
1151 11 zero_gravi 
    );
1152 2 zero_gravi 
    port (
1153 
      -- global control --
1154 
      clk_i       : in  std_ulogic; -- global clock, rising edge
1155 
      rstn_i      : in  std_ulogic; -- global reset, low-active, async
1156 
      ctrl_i      : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1157 
      -- data input --
1158 
      rs1_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1159 
      rs2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1160 
      pc2_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- delayed PC
1161 
      imm_i       : in  std_ulogic_vector(data_width_c-1 downto 0); -- immediate
1162 
      -- data output --
1163 
      res_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- ALU result
1164 36 zero_gravi 
      add_o       : out std_ulogic_vector(data_width_c-1 downto 0); -- address computation result
1165 2 zero_gravi 
      -- co-processor interface --
1166 49 zero_gravi 
      cp_start_o  : out std_ulogic_vector(7 downto 0); -- trigger co-processor i
1167 
      cp_valid_i  : in  std_ulogic_vector(7 downto 0); -- co-processor i done
1168 
      cp_result_i : in  cp_data_if_t; -- co-processor result
1169 2 zero_gravi 
      -- status --
1170 
      wait_o      : out std_ulogic -- busy due to iterative processing units
1171 
    );
1172 
  end component;
1173 
 
1174 44 zero_gravi 
  -- Component: CPU Co-Processor MULDIV ('M' extension) -------------------------------------
1175 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1176 
  component neorv32_cpu_cp_muldiv
1177 19 zero_gravi 
    generic (
1178 
      FAST_MUL_EN : boolean := false -- use DSPs for faster multiplication
1179 
    );
1180 2 zero_gravi 
    port (
1181 
      -- global control --
1182 
      clk_i   : in  std_ulogic; -- global clock, rising edge
1183 
      rstn_i  : in  std_ulogic; -- global reset, low-active, async
1184 
      ctrl_i  : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1185 36 zero_gravi 
      start_i : in  std_ulogic; -- trigger operation
1186 2 zero_gravi 
      -- data input --
1187 
      rs1_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1188 
      rs2_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1189 
      -- result and status --
1190 
      res_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
1191 
      valid_o : out std_ulogic -- data output valid
1192 
    );
1193 
  end component;
1194 
 
1195 44 zero_gravi 
  -- Component: CPU Co-Processor Bit Manipulation ('B' extension) ---------------------------
1196 
  -- -------------------------------------------------------------------------------------------
1197 
  component neorv32_cpu_cp_bitmanip
1198 
    port (
1199 
      -- global control --
1200 
      clk_i   : in  std_ulogic; -- global clock, rising edge
1201 
      rstn_i  : in  std_ulogic; -- global reset, low-active, async
1202 
      ctrl_i  : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1203 
      start_i : in  std_ulogic; -- trigger operation
1204 
      -- data input --
1205 
      cmp_i   : in  std_ulogic_vector(1 downto 0); -- comparator status
1206 
      rs1_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1207 
      rs2_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1208 
      -- result and status --
1209 
      res_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
1210 
      valid_o : out std_ulogic -- data output valid
1211 
    );
1212 
  end component;
1213 
 
1214 53 zero_gravi 
  -- Component: CPU Co-Processor 32-bit FPU ('Zfinx' extension) -----------------------------
1215 52 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1216 
  component neorv32_cpu_cp_fpu
1217 
    port (
1218 
      -- global control --
1219 53 zero_gravi 
      clk_i    : in  std_ulogic; -- global clock, rising edge
1220 
      rstn_i   : in  std_ulogic; -- global reset, low-active, async
1221 
      ctrl_i   : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1222 
      start_i  : in  std_ulogic; -- trigger operation
1223 52 zero_gravi 
      -- data input --
1224 53 zero_gravi 
      frm_i    : in  std_ulogic_vector(2 downto 0); -- rounding mode
1225 56 zero_gravi 
      cmp_i    : in  std_ulogic_vector(1 downto 0); -- comparator status
1226 53 zero_gravi 
      rs1_i    : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 1
1227 
      rs2_i    : in  std_ulogic_vector(data_width_c-1 downto 0); -- rf source 2
1228 52 zero_gravi 
      -- result and status --
1229 53 zero_gravi 
      res_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- operation result
1230 
      fflags_o : out std_ulogic_vector(4 downto 0); -- exception flags
1231 
      valid_o  : out std_ulogic -- data output valid
1232 52 zero_gravi 
    );
1233 
  end component;
1234 
 
1235 2 zero_gravi 
  -- Component: CPU Bus Interface -----------------------------------------------------------
1236 
  -- -------------------------------------------------------------------------------------------
1237 
  component neorv32_cpu_bus
1238 
    generic (
1239 53 zero_gravi 
      CPU_EXTENSION_RISCV_A : boolean := false; -- implement atomic extension?
1240 40 zero_gravi 
      CPU_EXTENSION_RISCV_C : boolean := true;  -- implement compressed extension?
1241 15 zero_gravi 
      -- Physical memory protection (PMP) --
1242 42 zero_gravi 
      PMP_NUM_REGIONS       : natural := 0;       -- number of regions (0..64)
1243 
      PMP_MIN_GRANULARITY   : natural := 64*1024; -- minimal region granularity in bytes, has to be a power of 2, min 8 bytes
1244 41 zero_gravi 
      -- Bus Timeout --
1245 
      BUS_TIMEOUT           : natural := 63     -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
1246 2 zero_gravi 
    );
1247 
    port (
1248 
      -- global control --
1249 12 zero_gravi 
      clk_i          : in  std_ulogic; -- global clock, rising edge
1250 38 zero_gravi 
      rstn_i      : in  std_ulogic := '0'; -- global reset, low-active, async
1251 12 zero_gravi 
      ctrl_i         : in  std_ulogic_vector(ctrl_width_c-1 downto 0); -- main control bus
1252 
      -- cpu instruction fetch interface --
1253 
      fetch_pc_i     : in  std_ulogic_vector(data_width_c-1 downto 0); -- PC for instruction fetch
1254 
      instr_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- instruction
1255 
      i_wait_o       : out std_ulogic; -- wait for fetch to complete
1256 
      --
1257 
      ma_instr_o     : out std_ulogic; -- misaligned instruction address
1258 
      be_instr_o     : out std_ulogic; -- bus error on instruction access
1259 
      -- cpu data access interface --
1260 
      addr_i         : in  std_ulogic_vector(data_width_c-1 downto 0); -- ALU result -> access address
1261 
      wdata_i        : in  std_ulogic_vector(data_width_c-1 downto 0); -- write data
1262 
      rdata_o        : out std_ulogic_vector(data_width_c-1 downto 0); -- read data
1263 
      mar_o          : out std_ulogic_vector(data_width_c-1 downto 0); -- current memory address register
1264 
      d_wait_o       : out std_ulogic; -- wait for access to complete
1265 
      --
1266 53 zero_gravi 
      bus_excl_ok_o  : out std_ulogic; -- bus exclusive access successful
1267 12 zero_gravi 
      ma_load_o      : out std_ulogic; -- misaligned load data address
1268 
      ma_store_o     : out std_ulogic; -- misaligned store data address
1269 
      be_load_o      : out std_ulogic; -- bus error on load data access
1270 
      be_store_o     : out std_ulogic; -- bus error on store data access
1271 15 zero_gravi 
      -- physical memory protection --
1272 
      pmp_addr_i     : in  pmp_addr_if_t; -- addresses
1273 
      pmp_ctrl_i     : in  pmp_ctrl_if_t; -- configs
1274 12 zero_gravi 
      -- instruction bus --
1275 
      i_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1276 
      i_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1277 
      i_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1278 
      i_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1279 
      i_bus_we_o     : out std_ulogic; -- write enable
1280 
      i_bus_re_o     : out std_ulogic; -- read enable
1281 
      i_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
1282 
      i_bus_ack_i    : in  std_ulogic; -- bus transfer acknowledge
1283 
      i_bus_err_i    : in  std_ulogic; -- bus transfer error
1284 
      i_bus_fence_o  : out std_ulogic; -- fence operation
1285 
      -- data bus --
1286 
      d_bus_addr_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1287 
      d_bus_rdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1288 
      d_bus_wdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1289 
      d_bus_ben_o    : out std_ulogic_vector(03 downto 0); -- byte enable
1290 
      d_bus_we_o     : out std_ulogic; -- write enable
1291 
      d_bus_re_o     : out std_ulogic; -- read enable
1292 
      d_bus_cancel_o : out std_ulogic; -- cancel current bus transaction
1293 
      d_bus_ack_i    : in  std_ulogic; -- bus transfer acknowledge
1294 
      d_bus_err_i    : in  std_ulogic; -- bus transfer error
1295 39 zero_gravi 
      d_bus_fence_o  : out std_ulogic; -- fence operation
1296 53 zero_gravi 
      d_bus_excl_o   : out std_ulogic; -- exclusive access request
1297 
      d_bus_excl_i   : in  std_ulogic  -- state of exclusiv access (set if success)
1298 2 zero_gravi 
    );
1299 
  end component;
1300 
 
1301 45 zero_gravi 
  -- Component: CPU Instruction Cache -------------------------------------------------------
1302 41 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1303 45 zero_gravi 
  component neorv32_icache
1304 41 zero_gravi 
    generic (
1305 47 zero_gravi 
      ICACHE_NUM_BLOCKS : natural := 4;  -- number of blocks (min 1), has to be a power of 2
1306 
      ICACHE_BLOCK_SIZE : natural := 16; -- block size in bytes (min 4), has to be a power of 2
1307 
      ICACHE_NUM_SETS   : natural := 1   -- associativity / number of sets (1=direct_mapped), has to be a power of 2
1308 41 zero_gravi 
    );
1309 
    port (
1310 
      -- global control --
1311 
      clk_i         : in  std_ulogic; -- global clock, rising edge
1312 
      rstn_i        : in  std_ulogic; -- global reset, low-active, async
1313 
      clear_i       : in  std_ulogic; -- cache clear
1314 
      -- host controller interface --
1315 
      host_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1316 
      host_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1317 
      host_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1318 
      host_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1319 
      host_we_i     : in  std_ulogic; -- write enable
1320 
      host_re_i     : in  std_ulogic; -- read enable
1321 
      host_cancel_i : in  std_ulogic; -- cancel current bus transaction
1322 
      host_ack_o    : out std_ulogic; -- bus transfer acknowledge
1323 
      host_err_o    : out std_ulogic; -- bus transfer error
1324 
      -- peripheral bus interface --
1325 
      bus_addr_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1326 
      bus_rdata_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1327 
      bus_wdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1328 
      bus_ben_o     : out std_ulogic_vector(03 downto 0); -- byte enable
1329 
      bus_we_o      : out std_ulogic; -- write enable
1330 
      bus_re_o      : out std_ulogic; -- read enable
1331 
      bus_cancel_o  : out std_ulogic; -- cancel current bus transaction
1332 
      bus_ack_i     : in  std_ulogic; -- bus transfer acknowledge
1333 
      bus_err_i     : in  std_ulogic  -- bus transfer error
1334 
    );
1335 
  end component;
1336 
 
1337 12 zero_gravi 
  -- Component: CPU Bus Switch --------------------------------------------------------------
1338 
  -- -------------------------------------------------------------------------------------------
1339 
  component neorv32_busswitch
1340 
    generic (
1341 
      PORT_CA_READ_ONLY : boolean := false; -- set if controller port A is read-only
1342 
      PORT_CB_READ_ONLY : boolean := false  -- set if controller port B is read-only
1343 
    );
1344 
    port (
1345 
      -- global control --
1346 
      clk_i           : in  std_ulogic; -- global clock, rising edge
1347 
      rstn_i          : in  std_ulogic; -- global reset, low-active, async
1348 
      -- controller interface a --
1349 
      ca_bus_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1350 
      ca_bus_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1351 
      ca_bus_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1352 
      ca_bus_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1353 
      ca_bus_we_i     : in  std_ulogic; -- write enable
1354 
      ca_bus_re_i     : in  std_ulogic; -- read enable
1355 
      ca_bus_cancel_i : in  std_ulogic; -- cancel current bus transaction
1356 53 zero_gravi 
      ca_bus_excl_i   : in  std_ulogic; -- exclusive access
1357 12 zero_gravi 
      ca_bus_ack_o    : out std_ulogic; -- bus transfer acknowledge
1358 
      ca_bus_err_o    : out std_ulogic; -- bus transfer error
1359 
      -- controller interface b --
1360 
      cb_bus_addr_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1361 
      cb_bus_rdata_o  : out std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1362 
      cb_bus_wdata_i  : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1363 
      cb_bus_ben_i    : in  std_ulogic_vector(03 downto 0); -- byte enable
1364 
      cb_bus_we_i     : in  std_ulogic; -- write enable
1365 
      cb_bus_re_i     : in  std_ulogic; -- read enable
1366 
      cb_bus_cancel_i : in  std_ulogic; -- cancel current bus transaction
1367 53 zero_gravi 
      cb_bus_excl_i   : in  std_ulogic; -- exclusive access
1368 12 zero_gravi 
      cb_bus_ack_o    : out std_ulogic; -- bus transfer acknowledge
1369 
      cb_bus_err_o    : out std_ulogic; -- bus transfer error
1370 
      -- peripheral bus --
1371 36 zero_gravi 
      p_bus_src_o     : out std_ulogic; -- access source: 0 = A, 1 = B
1372 12 zero_gravi 
      p_bus_addr_o    : out std_ulogic_vector(data_width_c-1 downto 0); -- bus access address
1373 
      p_bus_rdata_i   : in  std_ulogic_vector(data_width_c-1 downto 0); -- bus read data
1374 
      p_bus_wdata_o   : out std_ulogic_vector(data_width_c-1 downto 0); -- bus write data
1375 
      p_bus_ben_o     : out std_ulogic_vector(03 downto 0); -- byte enable
1376 
      p_bus_we_o      : out std_ulogic; -- write enable
1377 
      p_bus_re_o      : out std_ulogic; -- read enable
1378 
      p_bus_cancel_o  : out std_ulogic; -- cancel current bus transaction
1379 53 zero_gravi 
      p_bus_excl_o    : out std_ulogic; -- exclusive access
1380 12 zero_gravi 
      p_bus_ack_i     : in  std_ulogic; -- bus transfer acknowledge
1381 
      p_bus_err_i     : in  std_ulogic  -- bus transfer error
1382 
    );
1383 
  end component;
1384 
 
1385 2 zero_gravi 
  -- Component: CPU Compressed Instructions Decompressor ------------------------------------
1386 
  -- -------------------------------------------------------------------------------------------
1387 
  component neorv32_cpu_decompressor
1388 
    port (
1389 
      -- instruction input --
1390 
      ci_instr16_i : in  std_ulogic_vector(15 downto 0); -- compressed instruction input
1391 
      -- instruction output --
1392 
      ci_illegal_o : out std_ulogic; -- is an illegal compressed instruction
1393 
      ci_instr32_o : out std_ulogic_vector(31 downto 0)  -- 32-bit decompressed instruction
1394 
    );
1395 
  end component;
1396 
 
1397 
  -- Component: Processor-internal instruction memory (IMEM) --------------------------------
1398 
  -- -------------------------------------------------------------------------------------------
1399 
  component neorv32_imem
1400 
    generic (
1401 
      IMEM_BASE      : std_ulogic_vector(31 downto 0) := x"00000000"; -- memory base address
1402 
      IMEM_SIZE      : natural := 4*1024; -- processor-internal instruction memory size in bytes
1403 
      IMEM_AS_ROM    : boolean := false;  -- implement IMEM as read-only memory?
1404 44 zero_gravi 
      BOOTLOADER_EN  : boolean := true    -- implement and use bootloader?
1405 2 zero_gravi 
    );
1406 
    port (
1407 
      clk_i  : in  std_ulogic; -- global clock line
1408 
      rden_i : in  std_ulogic; -- read enable
1409 
      wren_i : in  std_ulogic; -- write enable
1410 
      ben_i  : in  std_ulogic_vector(03 downto 0); -- byte write enable
1411 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1412 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1413 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1414 
      ack_o  : out std_ulogic -- transfer acknowledge
1415 
    );
1416 
  end component;
1417 
 
1418 
  -- Component: Processor-internal data memory (DMEM) ---------------------------------------
1419 
  -- -------------------------------------------------------------------------------------------
1420 
  component neorv32_dmem
1421 
    generic (
1422 
      DMEM_BASE : std_ulogic_vector(31 downto 0) := x"80000000"; -- memory base address
1423 
      DMEM_SIZE : natural := 4*1024  -- processor-internal instruction memory size in bytes
1424 
    );
1425 
    port (
1426 
      clk_i  : in  std_ulogic; -- global clock line
1427 
      rden_i : in  std_ulogic; -- read enable
1428 
      wren_i : in  std_ulogic; -- write enable
1429 
      ben_i  : in  std_ulogic_vector(03 downto 0); -- byte write enable
1430 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1431 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1432 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1433 
      ack_o  : out std_ulogic -- transfer acknowledge
1434 
    );
1435 
  end component;
1436 
 
1437 
  -- Component: Processor-internal bootloader ROM (BOOTROM) ---------------------------------
1438 
  -- -------------------------------------------------------------------------------------------
1439 
  component neorv32_boot_rom
1440 23 zero_gravi 
    generic (
1441 
      BOOTROM_BASE : std_ulogic_vector(31 downto 0) := x"FFFF0000"; -- boot ROM base address
1442 
      BOOTROM_SIZE : natural := 4*1024  -- processor-internal boot ROM memory size in bytes
1443 
    );
1444 2 zero_gravi 
    port (
1445 
      clk_i  : in  std_ulogic; -- global clock line
1446 
      rden_i : in  std_ulogic; -- read enable
1447 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1448 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1449 
      ack_o  : out std_ulogic -- transfer acknowledge
1450 
    );
1451 
  end component;
1452 
 
1453 
  -- Component: Machine System Timer (mtime) ------------------------------------------------
1454 
  -- -------------------------------------------------------------------------------------------
1455 
  component neorv32_mtime
1456 
    port (
1457 
      -- host access --
1458 
      clk_i     : in  std_ulogic; -- global clock line
1459 4 zero_gravi 
      rstn_i    : in  std_ulogic := '0'; -- global reset, low-active, async
1460 2 zero_gravi 
      addr_i    : in  std_ulogic_vector(31 downto 0); -- address
1461 
      rden_i    : in  std_ulogic; -- read enable
1462 
      wren_i    : in  std_ulogic; -- write enable
1463 
      data_i    : in  std_ulogic_vector(31 downto 0); -- data in
1464 
      data_o    : out std_ulogic_vector(31 downto 0); -- data out
1465 
      ack_o     : out std_ulogic; -- transfer acknowledge
1466 11 zero_gravi 
      -- time output for CPU --
1467 
      time_o    : out std_ulogic_vector(63 downto 0); -- current system time
1468 2 zero_gravi 
      -- interrupt --
1469 
      irq_o     : out std_ulogic  -- interrupt request
1470 
    );
1471 
  end component;
1472 
 
1473 
  -- Component: General Purpose Input/Output Port (GPIO) ------------------------------------
1474 
  -- -------------------------------------------------------------------------------------------
1475 
  component neorv32_gpio
1476 
    port (
1477 
      -- host access --
1478 
      clk_i  : in  std_ulogic; -- global clock line
1479 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1480 
      rden_i : in  std_ulogic; -- read enable
1481 
      wren_i : in  std_ulogic; -- write enable
1482 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1483 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1484 
      ack_o  : out std_ulogic; -- transfer acknowledge
1485 
      -- parallel io --
1486 22 zero_gravi 
      gpio_o : out std_ulogic_vector(31 downto 0);
1487 
      gpio_i : in  std_ulogic_vector(31 downto 0);
1488 2 zero_gravi 
      -- interrupt --
1489 
      irq_o  : out std_ulogic
1490 
    );
1491 
  end component;
1492 
 
1493 
  -- Component: Watchdog Timer (WDT) --------------------------------------------------------
1494 
  -- -------------------------------------------------------------------------------------------
1495 
  component neorv32_wdt
1496 
    port (
1497 
      -- host access --
1498 
      clk_i       : in  std_ulogic; -- global clock line
1499 
      rstn_i      : in  std_ulogic; -- global reset line, low-active
1500 
      rden_i      : in  std_ulogic; -- read enable
1501 
      wren_i      : in  std_ulogic; -- write enable
1502 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1503 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1504 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1505 
      ack_o       : out std_ulogic; -- transfer acknowledge
1506 
      -- clock generator --
1507 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1508 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1509 
      -- timeout event --
1510 
      irq_o       : out std_ulogic; -- timeout IRQ
1511 
      rstn_o      : out std_ulogic  -- timeout reset, low_active, use it as async!
1512 
    );
1513 
  end component;
1514 
 
1515 
  -- Component: Universal Asynchronous Receiver and Transmitter (UART) ----------------------
1516 
  -- -------------------------------------------------------------------------------------------
1517 
  component neorv32_uart
1518 50 zero_gravi 
    generic (
1519 
      UART_PRIMARY : boolean := true -- true = primary UART (UART0), false = secondary UART (UART1)
1520 
    );
1521 2 zero_gravi 
    port (
1522 
      -- host access --
1523 
      clk_i       : in  std_ulogic; -- global clock line
1524 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1525 
      rden_i      : in  std_ulogic; -- read enable
1526 
      wren_i      : in  std_ulogic; -- write enable
1527 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1528 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1529 
      ack_o       : out std_ulogic; -- transfer acknowledge
1530 
      -- clock generator --
1531 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1532 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1533 
      -- com lines --
1534 
      uart_txd_o  : out std_ulogic;
1535 
      uart_rxd_i  : in  std_ulogic;
1536 51 zero_gravi 
      -- hardware flow control --
1537 
      uart_rts_o  : out std_ulogic; -- UART.RX ready to receive ("RTR"), low-active, optional
1538 
      uart_cts_i  : in  std_ulogic; -- UART.TX allowed to transmit, low-active, optional
1539 2 zero_gravi 
      -- interrupts --
1540 48 zero_gravi 
      irq_rxd_o   : out std_ulogic; -- uart data received interrupt
1541 
      irq_txd_o   : out std_ulogic  -- uart transmission done interrupt
1542 2 zero_gravi 
    );
1543 
  end component;
1544 
 
1545 
  -- Component: Serial Peripheral Interface (SPI) -------------------------------------------
1546 
  -- -------------------------------------------------------------------------------------------
1547 
  component neorv32_spi
1548 
    port (
1549 
      -- host access --
1550 
      clk_i       : in  std_ulogic; -- global clock line
1551 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1552 
      rden_i      : in  std_ulogic; -- read enable
1553 
      wren_i      : in  std_ulogic; -- write enable
1554 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1555 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1556 
      ack_o       : out std_ulogic; -- transfer acknowledge
1557 
      -- clock generator --
1558 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1559 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1560 
      -- com lines --
1561 6 zero_gravi 
      spi_sck_o   : out std_ulogic; -- SPI serial clock
1562 
      spi_sdo_o   : out std_ulogic; -- controller data out, peripheral data in
1563 
      spi_sdi_i   : in  std_ulogic; -- controller data in, peripheral data out
1564 2 zero_gravi 
      spi_csn_o   : out std_ulogic_vector(07 downto 0); -- SPI CS
1565 
      -- interrupt --
1566 48 zero_gravi 
      irq_o       : out std_ulogic -- transmission done interrupt
1567 2 zero_gravi 
    );
1568 
  end component;
1569 
 
1570 
  -- Component: Two-Wire Interface (TWI) ----------------------------------------------------
1571 
  -- -------------------------------------------------------------------------------------------
1572 
  component neorv32_twi
1573 
    port (
1574 
      -- host access --
1575 
      clk_i       : in  std_ulogic; -- global clock line
1576 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1577 
      rden_i      : in  std_ulogic; -- read enable
1578 
      wren_i      : in  std_ulogic; -- write enable
1579 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1580 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1581 
      ack_o       : out std_ulogic; -- transfer acknowledge
1582 
      -- clock generator --
1583 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1584 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1585 
      -- com lines --
1586 
      twi_sda_io  : inout std_logic; -- serial data line
1587 
      twi_scl_io  : inout std_logic; -- serial clock line
1588 
      -- interrupt --
1589 48 zero_gravi 
      irq_o       : out std_ulogic -- transfer done IRQ
1590 2 zero_gravi 
    );
1591 
  end component;
1592 
 
1593 
  -- Component: Pulse-Width Modulation Controller (PWM) -------------------------------------
1594 
  -- -------------------------------------------------------------------------------------------
1595 
  component neorv32_pwm
1596 
    port (
1597 
      -- host access --
1598 
      clk_i       : in  std_ulogic; -- global clock line
1599 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1600 
      rden_i      : in  std_ulogic; -- read enable
1601 
      wren_i      : in  std_ulogic; -- write enable
1602 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1603 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1604 
      ack_o       : out std_ulogic; -- transfer acknowledge
1605 
      -- clock generator --
1606 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1607 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1608 
      -- pwm output channels --
1609 
      pwm_o       : out std_ulogic_vector(03 downto 0)
1610 
    );
1611 
  end component;
1612 
 
1613 
  -- Component: True Random Number Generator (TRNG) -----------------------------------------
1614 
  -- -------------------------------------------------------------------------------------------
1615 
  component neorv32_trng
1616 
    port (
1617 
      -- host access --
1618 
      clk_i  : in  std_ulogic; -- global clock line
1619 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1620 
      rden_i : in  std_ulogic; -- read enable
1621 
      wren_i : in  std_ulogic; -- write enable
1622 
      data_i : in  std_ulogic_vector(31 downto 0); -- data in
1623 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1624 
      ack_o  : out std_ulogic  -- transfer acknowledge
1625 
    );
1626 
  end component;
1627 
 
1628 
  -- Component: Wishbone Bus Gateway (WISHBONE) ---------------------------------------------
1629 
  -- -------------------------------------------------------------------------------------------
1630 
  component neorv32_wishbone
1631 
    generic (
1632 35 zero_gravi 
      WB_PIPELINED_MODE : boolean := false; -- false: classic/standard wishbone mode, true: pipelined wishbone mode
1633 23 zero_gravi 
      -- Internal instruction memory --
1634 44 zero_gravi 
      MEM_INT_IMEM_EN   : boolean := true;   -- implement processor-internal instruction memory
1635 35 zero_gravi 
      MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
1636 23 zero_gravi 
      -- Internal data memory --
1637 44 zero_gravi 
      MEM_INT_DMEM_EN   : boolean := true;   -- implement processor-internal data memory
1638 35 zero_gravi 
      MEM_INT_DMEM_SIZE : natural := 4*1024  -- size of processor-internal data memory in bytes
1639 2 zero_gravi 
    );
1640 
    port (
1641 
      -- global control --
1642 53 zero_gravi 
      clk_i    : in  std_ulogic; -- global clock line
1643 
      rstn_i   : in  std_ulogic; -- global reset line, low-active
1644 2 zero_gravi 
      -- host access --
1645 53 zero_gravi 
      src_i    : in  std_ulogic; -- access type (0: data, 1:instruction)
1646 
      addr_i   : in  std_ulogic_vector(31 downto 0); -- address
1647 
      rden_i   : in  std_ulogic; -- read enable
1648 
      wren_i   : in  std_ulogic; -- write enable
1649 
      ben_i    : in  std_ulogic_vector(03 downto 0); -- byte write enable
1650 
      data_i   : in  std_ulogic_vector(31 downto 0); -- data in
1651 
      data_o   : out std_ulogic_vector(31 downto 0); -- data out
1652 
      cancel_i : in  std_ulogic; -- cancel current bus transaction
1653 
      excl_i   : in  std_ulogic; -- exclusive access request
1654 
      excl_o   : out std_ulogic; -- state of exclusiv access (set if success)
1655 
      ack_o    : out std_ulogic; -- transfer acknowledge
1656 
      err_o    : out std_ulogic; -- transfer error
1657 
      priv_i   : in  std_ulogic_vector(01 downto 0); -- current CPU privilege level
1658 2 zero_gravi 
      -- wishbone interface --
1659 53 zero_gravi 
      wb_tag_o : out std_ulogic_vector(03 downto 0); -- request tag
1660 
      wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
1661 
      wb_dat_i : in  std_ulogic_vector(31 downto 0); -- read data
1662 
      wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
1663 
      wb_we_o  : out std_ulogic; -- read/write
1664 
      wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
1665 
      wb_stb_o : out std_ulogic; -- strobe
1666 
      wb_cyc_o : out std_ulogic; -- valid cycle
1667 
      wb_tag_i : in  std_ulogic; -- response tag
1668 
      wb_ack_i : in  std_ulogic; -- transfer acknowledge
1669 
      wb_err_i : in  std_ulogic  -- transfer error
1670 2 zero_gravi 
    );
1671 
  end component;
1672 
 
1673 47 zero_gravi 
  -- Component: Custom Functions Subsystem (CFS) --------------------------------------------
1674 23 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1675 47 zero_gravi 
  component neorv32_cfs
1676 
    generic (
1677 52 zero_gravi 
      CFS_CONFIG   : std_ulogic_vector(31 downto 0); -- custom CFS configuration generic
1678 
      CFS_IN_SIZE  : positive := 32;  -- size of CFS input conduit in bits
1679 
      CFS_OUT_SIZE : positive := 32   -- size of CFS output conduit in bits
1680 23 zero_gravi 
    );
1681 34 zero_gravi 
    port (
1682 
      -- host access --
1683 
      clk_i       : in  std_ulogic; -- global clock line
1684 
      rstn_i      : in  std_ulogic; -- global reset line, low-active, use as async
1685 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1686 
      rden_i      : in  std_ulogic; -- read enable
1687 47 zero_gravi 
      wren_i      : in  std_ulogic; -- word write enable
1688 34 zero_gravi 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1689 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1690 
      ack_o       : out std_ulogic; -- transfer acknowledge
1691 
      -- clock generator --
1692 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1693 47 zero_gravi 
      clkgen_i    : in  std_ulogic_vector(07 downto 0); -- "clock" inputs
1694 
      -- CPU state --
1695 
      sleep_i     : in  std_ulogic; -- set if cpu is in sleep mode
1696 
      -- interrupt --
1697 
      irq_o       : out std_ulogic; -- interrupt request
1698 
      irq_ack_i   : in  std_ulogic; -- interrupt acknowledge
1699 
      -- custom io (conduit) --
1700 52 zero_gravi 
      cfs_in_i    : in  std_ulogic_vector(CFS_IN_SIZE-1 downto 0);  -- custom inputs
1701 
      cfs_out_o   : out std_ulogic_vector(CFS_OUT_SIZE-1 downto 0)  -- custom outputs
1702 34 zero_gravi 
    );
1703 
  end component;
1704 
 
1705 49 zero_gravi 
  -- Component: Numerically-Controlled Oscillator (NCO) -------------------------------------
1706 
  -- -------------------------------------------------------------------------------------------
1707 
  component neorv32_nco
1708 
    port (
1709 
      -- host access --
1710 
      clk_i       : in  std_ulogic; -- global clock line
1711 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1712 
      rden_i      : in  std_ulogic; -- read enable
1713 
      wren_i      : in  std_ulogic; -- write enable
1714 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1715 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1716 
      ack_o       : out std_ulogic; -- transfer acknowledge
1717 
      -- clock generator --
1718 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1719 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1720 
      -- NCO output --
1721 
      nco_o       : out std_ulogic_vector(02 downto 0)
1722 
    );
1723 
  end component;
1724 
 
1725 52 zero_gravi 
  -- Component: Smart LED (WS2811/WS2812) Interface (NEOLED) --------------------------------
1726 
  -- -------------------------------------------------------------------------------------------
1727 
  component neorv32_neoled
1728 
    port (
1729 
      -- host access --
1730 
      clk_i       : in  std_ulogic; -- global clock line
1731 
      addr_i      : in  std_ulogic_vector(31 downto 0); -- address
1732 
      rden_i      : in  std_ulogic; -- read enable
1733 
      wren_i      : in  std_ulogic; -- write enable
1734 
      data_i      : in  std_ulogic_vector(31 downto 0); -- data in
1735 
      data_o      : out std_ulogic_vector(31 downto 0); -- data out
1736 
      ack_o       : out std_ulogic; -- transfer acknowledge
1737 
      -- clock generator --
1738 
      clkgen_en_o : out std_ulogic; -- enable clock generator
1739 
      clkgen_i    : in  std_ulogic_vector(07 downto 0);
1740 
      -- interrupt --
1741 
      irq_o       : out std_ulogic; -- interrupt request
1742 
      -- NEOLED output --
1743 
      neoled_o    : out std_ulogic -- serial async data line
1744 
    );
1745 
  end component;
1746 
 
1747 23 zero_gravi 
  -- Component: System Configuration Information Memory (SYSINFO) ---------------------------
1748 
  -- -------------------------------------------------------------------------------------------
1749 12 zero_gravi 
  component neorv32_sysinfo
1750 
    generic (
1751 
      -- General --
1752 41 zero_gravi 
      CLOCK_FREQUENCY      : natural := 0;      -- clock frequency of clk_i in Hz
1753 44 zero_gravi 
      BOOTLOADER_EN        : boolean := true;   -- implement processor-internal bootloader?
1754 41 zero_gravi 
      USER_CODE            : std_ulogic_vector(31 downto 0) := x"00000000"; -- custom user code
1755 23 zero_gravi 
      -- Internal Instruction memory --
1756 44 zero_gravi 
      MEM_INT_IMEM_EN      : boolean := true;   -- implement processor-internal instruction memory
1757 41 zero_gravi 
      MEM_INT_IMEM_SIZE    : natural := 8*1024; -- size of processor-internal instruction memory in bytes
1758 
      MEM_INT_IMEM_ROM     : boolean := false;  -- implement processor-internal instruction memory as ROM
1759 23 zero_gravi 
      -- Internal Data memory --
1760 44 zero_gravi 
      MEM_INT_DMEM_EN      : boolean := true;   -- implement processor-internal data memory
1761 41 zero_gravi 
      MEM_INT_DMEM_SIZE    : natural := 4*1024; -- size of processor-internal data memory in bytes
1762 
      -- Internal Cache memory --
1763 44 zero_gravi 
      ICACHE_EN            : boolean := true;   -- implement instruction cache
1764 41 zero_gravi 
      ICACHE_NUM_BLOCKS    : natural := 4;      -- i-cache: number of blocks (min 2), has to be a power of 2
1765 
      ICACHE_BLOCK_SIZE    : natural := 64;     -- i-cache: block size in bytes (min 4), has to be a power of 2
1766 
      ICACHE_ASSOCIATIVITY : natural := 1;      -- i-cache: associativity (min 1), has to be a power 2
1767 23 zero_gravi 
      -- External memory interface --
1768 44 zero_gravi 
      MEM_EXT_EN           : boolean := false;  -- implement external memory bus interface?
1769 12 zero_gravi 
      -- Processor peripherals --
1770 44 zero_gravi 
      IO_GPIO_EN           : boolean := true;   -- implement general purpose input/output port unit (GPIO)?
1771 
      IO_MTIME_EN          : boolean := true;   -- implement machine system timer (MTIME)?
1772 50 zero_gravi 
      IO_UART0_EN          : boolean := true;   -- implement primary universal asynchronous receiver/transmitter (UART0)?
1773 
      IO_UART1_EN          : boolean := true;   -- implement secondary universal asynchronous receiver/transmitter (UART1)?
1774 44 zero_gravi 
      IO_SPI_EN            : boolean := true;   -- implement serial peripheral interface (SPI)?
1775 
      IO_TWI_EN            : boolean := true;   -- implement two-wire interface (TWI)?
1776 
      IO_PWM_EN            : boolean := true;   -- implement pulse-width modulation unit (PWM)?
1777 
      IO_WDT_EN            : boolean := true;   -- implement watch dog timer (WDT)?
1778 
      IO_TRNG_EN           : boolean := true;   -- implement true random number generator (TRNG)?
1779 49 zero_gravi 
      IO_CFS_EN            : boolean := true;   -- implement custom functions subsystem (CFS)?
1780 52 zero_gravi 
      IO_NCO_EN            : boolean := true;   -- implement numerically-controlled oscillator (NCO)?
1781 
      IO_NEOLED_EN         : boolean := true    -- implement NeoPixel-compatible smart LED interface (NEOLED)?
1782 12 zero_gravi 
    );
1783 
    port (
1784 
      -- host access --
1785 
      clk_i  : in  std_ulogic; -- global clock line
1786 
      addr_i : in  std_ulogic_vector(31 downto 0); -- address
1787 
      rden_i : in  std_ulogic; -- read enable
1788 
      data_o : out std_ulogic_vector(31 downto 0); -- data out
1789 
      ack_o  : out std_ulogic  -- transfer acknowledge
1790 
    );
1791 
  end component;
1792 
 
1793 2 zero_gravi 
end neorv32_package;
1794 
 
1795 
package body neorv32_package is
1796 
 
1797 41 zero_gravi 
  -- Function: Minimal required number of bits to represent input number --------------------
1798 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1799 
  function index_size_f(input : natural) return natural is
1800 
  begin
1801 
    for i in 0 to natural'high loop
1802 
      if (2**i >= input) then
1803 
        return i;
1804 
      end if;
1805 
    end loop; -- i
1806 
    return 0;
1807 
  end function index_size_f;
1808 
 
1809 
  -- Function: Conditional select natural ---------------------------------------------------
1810 
  -- -------------------------------------------------------------------------------------------
1811 
  function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural is
1812 
  begin
1813 
    if (cond = true) then
1814 
      return val_t;
1815 
    else
1816 
      return val_f;
1817 
    end if;
1818 
  end function cond_sel_natural_f;
1819 
 
1820 56 zero_gravi 
  -- Function: Conditional select integer ---------------------------------------------------
1821 
  -- -------------------------------------------------------------------------------------------
1822 
  function cond_sel_int_f(cond : boolean; val_t : integer; val_f : integer) return integer is
1823 
  begin
1824 
    if (cond = true) then
1825 
      return val_t;
1826 
    else
1827 
      return val_f;
1828 
    end if;
1829 
  end function cond_sel_int_f;
1830 
 
1831 2 zero_gravi 
  -- Function: Conditional select std_ulogic_vector -----------------------------------------
1832 
  -- -------------------------------------------------------------------------------------------
1833 
  function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector is
1834 
  begin
1835 
    if (cond = true) then
1836 
      return val_t;
1837 
    else
1838 
      return val_f;
1839 
    end if;
1840 
  end function cond_sel_stdulogicvector_f;
1841 
 
1842 56 zero_gravi 
  -- Function: Conditional select std_ulogic ------------------------------------------------
1843 
  -- -------------------------------------------------------------------------------------------
1844 
  function cond_sel_stdulogic_f(cond : boolean; val_t : std_ulogic; val_f : std_ulogic) return std_ulogic is
1845 
  begin
1846 
    if (cond = true) then
1847 
      return val_t;
1848 
    else
1849 
      return val_f;
1850 
    end if;
1851 
  end function cond_sel_stdulogic_f;
1852 
 
1853 50 zero_gravi 
  -- Function: Conditional select string ----------------------------------------------------
1854 2 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1855 50 zero_gravi 
  function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string is
1856 
  begin
1857 
    if (cond = true) then
1858 
      return val_t;
1859 
    else
1860 
      return val_f;
1861 
    end if;
1862 
  end function cond_sel_string_f;
1863 
 
1864 
  -- Function: Convert bool to std_ulogic ---------------------------------------------------
1865 
  -- -------------------------------------------------------------------------------------------
1866 2 zero_gravi 
  function bool_to_ulogic_f(cond : boolean) return std_ulogic is
1867 
  begin
1868 
    if (cond = true) then
1869 
      return '1';
1870 
    else
1871 
      return '0';
1872 
    end if;
1873 
  end function bool_to_ulogic_f;
1874 
 
1875 
  -- Function: OR all bits ------------------------------------------------------------------
1876 
  -- -------------------------------------------------------------------------------------------
1877 
  function or_all_f(a : std_ulogic_vector) return std_ulogic is
1878 
    variable tmp_v : std_ulogic;
1879 
  begin
1880 56 zero_gravi 
    tmp_v := '0';
1881 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1882 56 zero_gravi 
      for i in a'low to a'high loop
1883 15 zero_gravi 
        tmp_v := tmp_v or a(i);
1884 
      end loop; -- i
1885 
    end if;
1886 2 zero_gravi 
    return tmp_v;
1887 
  end function or_all_f;
1888 
 
1889 
  -- Function: AND all bits -----------------------------------------------------------------
1890 
  -- -------------------------------------------------------------------------------------------
1891 
  function and_all_f(a : std_ulogic_vector) return std_ulogic is
1892 
    variable tmp_v : std_ulogic;
1893 
  begin
1894 56 zero_gravi 
    tmp_v := '1';
1895 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1896 56 zero_gravi 
      for i in a'low to a'high loop
1897 15 zero_gravi 
        tmp_v := tmp_v and a(i);
1898 
      end loop; -- i
1899 
    end if;
1900 2 zero_gravi 
    return tmp_v;
1901 
  end function and_all_f;
1902 
 
1903 
  -- Function: XOR all bits -----------------------------------------------------------------
1904 
  -- -------------------------------------------------------------------------------------------
1905 
  function xor_all_f(a : std_ulogic_vector) return std_ulogic is
1906 
    variable tmp_v : std_ulogic;
1907 
  begin
1908 56 zero_gravi 
    tmp_v := '0';
1909 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1910 56 zero_gravi 
      for i in a'low to a'high loop
1911 15 zero_gravi 
        tmp_v := tmp_v xor a(i);
1912 
      end loop; -- i
1913 
    end if;
1914 2 zero_gravi 
    return tmp_v;
1915 
  end function xor_all_f;
1916 
 
1917 
  -- Function: XNOR all bits ----------------------------------------------------------------
1918 
  -- -------------------------------------------------------------------------------------------
1919 
  function xnor_all_f(a : std_ulogic_vector) return std_ulogic is
1920 
    variable tmp_v : std_ulogic;
1921 
  begin
1922 56 zero_gravi 
    tmp_v := '1';
1923 15 zero_gravi 
    if (a'low < a'high) then -- not null range?
1924 56 zero_gravi 
      for i in a'low to a'high loop
1925 15 zero_gravi 
        tmp_v := tmp_v xnor a(i);
1926 
      end loop; -- i
1927 
    end if;
1928 2 zero_gravi 
    return tmp_v;
1929 
  end function xnor_all_f;
1930 
 
1931 40 zero_gravi 
  -- Function: Convert std_ulogic_vector to hex char ----------------------------------------
1932 6 zero_gravi 
  -- -------------------------------------------------------------------------------------------
1933 
  function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character is
1934 
    variable output_v : character;
1935 
  begin
1936 
    case input is
1937 7 zero_gravi 
      when x"0"   => output_v := '0';
1938 
      when x"1"   => output_v := '1';
1939 
      when x"2"   => output_v := '2';
1940 
      when x"3"   => output_v := '3';
1941 
      when x"4"   => output_v := '4';
1942 
      when x"5"   => output_v := '5';
1943 
      when x"6"   => output_v := '6';
1944 
      when x"7"   => output_v := '7';
1945 
      when x"8"   => output_v := '8';
1946 
      when x"9"   => output_v := '9';
1947 
      when x"a"   => output_v := 'a';
1948 
      when x"b"   => output_v := 'b';
1949 
      when x"c"   => output_v := 'c';
1950 
      when x"d"   => output_v := 'd';
1951 
      when x"e"   => output_v := 'e';
1952 
      when x"f"   => output_v := 'f';
1953 6 zero_gravi 
      when others => output_v := '?';
1954 
    end case;
1955 
    return output_v;
1956 
  end function to_hexchar_f;
1957 
 
1958 40 zero_gravi 
  -- Function: Convert hex char to std_ulogic_vector ----------------------------------------
1959 
  -- -------------------------------------------------------------------------------------------
1960 
  function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector is
1961 
    variable hex_value_v : std_ulogic_vector(3 downto 0);
1962 
  begin
1963 
    case input is
1964 
      when '0'       => hex_value_v := x"0";
1965 
      when '1'       => hex_value_v := x"1";
1966 
      when '2'       => hex_value_v := x"2";
1967 
      when '3'       => hex_value_v := x"3";
1968 
      when '4'       => hex_value_v := x"4";
1969 
      when '5'       => hex_value_v := x"5";
1970 
      when '6'       => hex_value_v := x"6";
1971 
      when '7'       => hex_value_v := x"7";
1972 
      when '8'       => hex_value_v := x"8";
1973 
      when '9'       => hex_value_v := x"9";
1974 
      when 'a' | 'A' => hex_value_v := x"a";
1975 
      when 'b' | 'B' => hex_value_v := x"b";
1976 
      when 'c' | 'C' => hex_value_v := x"c";
1977 
      when 'd' | 'D' => hex_value_v := x"d";
1978 
      when 'e' | 'E' => hex_value_v := x"e";
1979 
      when 'f' | 'F' => hex_value_v := x"f";
1980 
      when others    => hex_value_v := (others => 'X');
1981 
    end case;
1982 
    return hex_value_v;
1983 
  end function hexchar_to_stdulogicvector_f;
1984 
 
1985 32 zero_gravi 
  -- Function: Bit reversal -----------------------------------------------------------------
1986 
  -- -------------------------------------------------------------------------------------------
1987 
  function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector is
1988 
    variable output_v : std_ulogic_vector(input'range);
1989 
  begin
1990 
    for i in 0 to input'length-1 loop
1991 
      output_v(input'length-i-1) := input(i);
1992 
    end loop; -- i
1993 
    return output_v;
1994 
  end function bit_rev_f;
1995 
 
1996 36 zero_gravi 
  -- Function: Test if input number is a power of two ---------------------------------------
1997 
  -- -------------------------------------------------------------------------------------------
1998 
  function is_power_of_two_f(input : natural) return boolean is
1999 
  begin
2000 38 zero_gravi 
    if (input = 1) then -- 2^0
2001 36 zero_gravi 
      return true;
2002 38 zero_gravi 
    elsif ((input / 2) /= 0) and ((input mod 2) = 0) then
2003 
      return true;
2004 36 zero_gravi 
    else
2005 
      return false;
2006 
    end if;
2007 
  end function is_power_of_two_f;
2008 
 
2009 40 zero_gravi 
  -- Function: Swap all bytes of a 32-bit word (endianness conversion) ----------------------
2010 
  -- -------------------------------------------------------------------------------------------
2011 
  function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector is
2012 
    variable output_v : std_ulogic_vector(input'range);
2013 
  begin
2014 
    output_v(07 downto 00) := input(31 downto 24);
2015 
    output_v(15 downto 08) := input(23 downto 16);
2016 
    output_v(23 downto 16) := input(15 downto 08);
2017 
    output_v(31 downto 24) := input(07 downto 00);
2018 
    return output_v;
2019 
  end function bswap32_f;
2020 
 
2021 2 zero_gravi 
end neorv32_package;

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