Subversion Repositories neorv32

-- #################################################################################################

-- # << NEORV32 - Main VHDL package file >>                                                        #

-- # ********************************************************************************************* #

-- # BSD 3-Clause License                                                                          #

-- #                                                                                               #

-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #

-- #                                                                                               #

-- # Redistribution and use in source and binary forms, with or without modification, are          #

-- # permitted provided that the following conditions are met:                                     #

-- #                                                                                               #

-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #

-- #    conditions and the following disclaimer.                                                   #

-- #                                                                                               #

-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #

-- #    conditions and the following disclaimer in the documentation and/or other materials        #

-- #    provided with the distribution.                                                            #

-- #                                                                                               #

-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #

-- #    endorse or promote products derived from this software without specific prior written      #

-- #    permission.                                                                                #

-- #                                                                                               #

-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #

-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #

-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #

-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #

-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #

-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #

-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #

-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #

-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #

-- # ********************************************************************************************* #

-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #

-- #################################################################################################

library ieee;

use ieee.std_logic_1164.all;

use ieee.numeric_std.all;

package neorv32_package is

  -- Architecture Configuration -------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- address space --

  constant ispace_base_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- default instruction memory address space base address

  constant dspace_base_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- default data memory address space base address

  -- (external) bus interface --

  constant wb_pipe_mode_c    : boolean := false; -- *external* bus protocol: false=classic/standard wishbone mode (default), true=pipelined wishbone mode

  constant xbus_big_endian_c : boolean := true; -- external memory access byte order: true=big endian (default); false=little endian

  -- CPU core --

  constant ipb_entries_c     : natural := 4; -- entries in CPU instruction prefetch buffer, has to be a power of 2, default=2

  constant cp_timeout_en_c   : boolean := false; -- auto-terminate pending co-processor operations after 256 cycles (for debugging only), default = false

  constant dedicated_reset_c : boolean := false; -- use dedicated hardware reset value for UNCRITICAL registers (FALSE=reset value is irrelevant (might simplify HW), default; TRUE=defined LOW reset value)

  -- "critical" number of implemented PMP regions --

  -- if more PMP regions (> pmp_num_regions_critical_c) are defined, another register stage is automatically inserted into the memory interfaces

  -- increasing instruction fetch & data access latency by +1 cycle but also reducing critical path length

  constant pmp_num_regions_critical_c : natural := 8; -- default=8

  -- "response time window" for processor-internal memories and IO devices

  constant max_proc_int_response_time_c : natural := 15; -- cycles after which an *unacknowledged* internal bus access will timeout and trigger a bus fault exception (min 2)

  -- jtag tap - identifier --

  constant jtag_tap_idcode_version_c : std_ulogic_vector(03 downto 0) := x"0"; -- version

  constant jtag_tap_idcode_partid_c  : std_ulogic_vector(15 downto 0) := x"cafe"; -- part number

  constant jtag_tap_idcode_manid_c   : std_ulogic_vector(10 downto 0) := "00000000000"; -- manufacturer id

  -- Helper Functions -----------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  function index_size_f(input : natural) return natural;

  function cond_sel_natural_f(cond : boolean; val_t : natural; val_f : natural) return natural;

  function cond_sel_int_f(cond : boolean; val_t : integer; val_f : integer) return integer;

  function cond_sel_stdulogicvector_f(cond : boolean; val_t : std_ulogic_vector; val_f : std_ulogic_vector) return std_ulogic_vector;

  function cond_sel_stdulogic_f(cond : boolean; val_t : std_ulogic; val_f : std_ulogic) return std_ulogic;

  function cond_sel_string_f(cond : boolean; val_t : string; val_f : string) return string;

  function bool_to_ulogic_f(cond : boolean) return std_ulogic;

  function or_all_f(a : std_ulogic_vector) return std_ulogic;

  function and_all_f(a : std_ulogic_vector) return std_ulogic;

  function xor_all_f(a : std_ulogic_vector) return std_ulogic;

  function xnor_all_f(a : std_ulogic_vector) return std_ulogic;

  function to_hexchar_f(input : std_ulogic_vector(3 downto 0)) return character;

  function hexchar_to_stdulogicvector_f(input : character) return std_ulogic_vector;

  function bit_rev_f(input : std_ulogic_vector) return std_ulogic_vector;

  function is_power_of_two_f(input : natural) return boolean;

  function bswap32_f(input : std_ulogic_vector) return std_ulogic_vector;

  -- Architecture Constants (do not modify!) ------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  constant data_width_c   : natural := 32; -- native data path width - do not change!

  constant hw_version_c   : std_ulogic_vector(31 downto 0) := x"01050509"; -- no touchy!

  constant archid_c       : natural := 19; -- official NEORV32 architecture ID - hands off!

  constant rf_r0_is_reg_c : boolean := true; -- x0 is a *physical register* that has to be initialized to zero by the CPU

  constant def_rst_val_c  : std_ulogic := cond_sel_stdulogic_f(dedicated_reset_c, '0', '-');

  -- Internal Types -------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  type pmp_ctrl_if_t is array (0 to 63) of std_ulogic_vector(07 downto 0);

  type pmp_addr_if_t is array (0 to 63) of std_ulogic_vector(33 downto 0);

  type cp_data_if_t  is array (0 to 7)  of std_ulogic_vector(data_width_c-1 downto 0);

  -- Processor-Internal Address Space Layout ------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- Internal Instruction Memory (IMEM) and Date Memory (DMEM) --

  constant imem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := ispace_base_c; -- internal instruction memory base address

  constant dmem_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := dspace_base_c; -- internal data memory base address

  --> internal data/instruction memory sizes are configured via top's generics

  -- Internal Bootloader ROM --

  constant boot_rom_base_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffff0000"; -- bootloader base address, fixed!

  constant boot_rom_size_c      : natural := 4*1024; -- module's address space in bytes

  constant boot_rom_max_size_c  : natural := 32*1024; -- max module's address space in bytes, fixed!

  -- On-Chip Debugger: Debug Module --

  constant dm_base_c            : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff800"; -- base address, fixed!

  constant dm_size_c            : natural := 4*32*4; -- debug ROM address space in bytes, fixed

  constant dm_code_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff800";

  constant dm_pbuf_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff880";

  constant dm_data_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff900";

  constant dm_sreg_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"fffff980";

  -- IO: Peripheral Devices ("IO") Area --

  -- Control register(s) (including the device-enable) should be located at the base address of each device

  constant io_base_c            : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff00";

  constant io_size_c            : natural := 64*4; -- module's address space in bytes, fixed!

  -- Custom Functions Subsystem (CFS) --

  constant cfs_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff00"; -- base address

  constant cfs_size_c           : natural := 32*4; -- module's address space in bytes

  constant cfs_reg0_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff00";

  constant cfs_reg1_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff04";

  constant cfs_reg2_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff08";

  constant cfs_reg3_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff0c";

  constant cfs_reg4_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff10";

  constant cfs_reg5_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff14";

  constant cfs_reg6_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff18";

  constant cfs_reg7_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff1c";

  constant cfs_reg8_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff20";

  constant cfs_reg9_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff24";

  constant cfs_reg10_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff28";

  constant cfs_reg11_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff2c";

  constant cfs_reg12_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff30";

  constant cfs_reg13_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff34";

  constant cfs_reg14_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff38";

  constant cfs_reg15_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff3c";

  constant cfs_reg16_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff40";

  constant cfs_reg17_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff44";

  constant cfs_reg18_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff48";

  constant cfs_reg19_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff4c";

  constant cfs_reg20_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff50";

  constant cfs_reg21_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff54";

  constant cfs_reg22_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff58";

  constant cfs_reg23_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff5c";

  constant cfs_reg24_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff60";

  constant cfs_reg25_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff64";

  constant cfs_reg26_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff68";

  constant cfs_reg27_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff6c";

  constant cfs_reg28_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff70";

  constant cfs_reg29_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff74";

  constant cfs_reg30_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff78";

  constant cfs_reg31_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff7c";

  -- General Purpose Input/Output Unit (GPIO) --

  constant gpio_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff80"; -- base address

  constant gpio_size_c          : natural := 2*4; -- module's address space in bytes

  constant gpio_in_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff80";

  constant gpio_out_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff84";

  -- True Random Number Generator (TRNG) --

  constant trng_base_c          : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff88"; -- base address

  constant trng_size_c          : natural := 1*4; -- module's address space in bytes

  constant trng_ctrl_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff88";

  -- Watch Dog Timer (WDT) --

  constant wdt_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff8c"; -- base address

  constant wdt_size_c           : natural := 1*4; -- module's address space in bytes

  constant wdt_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff8c";

  -- Machine System Timer (MTIME) --

  constant mtime_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff90"; -- base address

  constant mtime_size_c         : natural := 4*4; -- module's address space in bytes

  constant mtime_time_lo_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff90";

  constant mtime_time_hi_addr_c : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff94";

  constant mtime_cmp_lo_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff98";

  constant mtime_cmp_hi_addr_c  : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffff9c";

  -- Primary Universal Asynchronous Receiver/Transmitter (UART0) --

  constant uart0_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa0"; -- base address

  constant uart0_size_c         : natural := 2*4; -- module's address space in bytes

  constant uart0_ctrl_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa0";

  constant uart0_rtx_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa4";

  -- Serial Peripheral Interface (SPI) --

  constant spi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa8"; -- base address

  constant spi_size_c           : natural := 2*4; -- module's address space in bytes

  constant spi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffa8";

  constant spi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffac";

  -- Two Wire Interface (TWI) --

  constant twi_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb0"; -- base address

  constant twi_size_c           : natural := 2*4; -- module's address space in bytes

  constant twi_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb0";

  constant twi_rtx_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb4";

  -- Pulse-Width Modulation Controller (PWM) --

  constant pwm_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb8"; -- base address

  constant pwm_size_c           : natural := 2*4; -- module's address space in bytes

  constant pwm_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffb8";

  constant pwm_duty_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffbc";

  -- Numerically-Controlled Oscillator (NCO) --

  constant nco_base_c           : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc0"; -- base address

  constant nco_size_c           : natural := 4*4; -- module's address space in bytes

  constant nco_ctrl_addr_c      : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc0";

  constant nco_ch0_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc4";

  constant nco_ch1_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffc8";

  constant nco_ch2_addr_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffcc";

  -- Secondary Universal Asynchronous Receiver/Transmitter (UART1) --

  constant uart1_base_c         : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd0"; -- base address

  constant uart1_size_c         : natural := 2*4; -- module's address space in bytes

  constant uart1_ctrl_addr_c    : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd0";

  constant uart1_rtx_addr_c     : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd4";

  -- Smart LED (WS2811/WS2812) Interface (NEOLED) --

  constant neoled_base_c        : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd8"; -- base address

  constant neoled_size_c        : natural := 2*4; -- module's address space in bytes

  constant neoled_ctrl_addr_c   : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffd8";

  constant neoled_data_addr_c   : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffdc";

  -- System Information Memory (SYSINFO) --

  constant sysinfo_base_c       : std_ulogic_vector(data_width_c-1 downto 0) := x"ffffffe0"; -- base address

  constant sysinfo_size_c       : natural := 8*4; -- module's address space in bytes

  -- Main CPU Control Bus -------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- register file --

  constant ctrl_rf_in_mux_c     : natural :=  0; -- input source select lsb (0=MEM, 1=ALU)

  constant ctrl_rf_rs1_adr0_c   : natural :=  1; -- source register 1 address bit 0

  constant ctrl_rf_rs1_adr1_c   : natural :=  2; -- source register 1 address bit 1

  constant ctrl_rf_rs1_adr2_c   : natural :=  3; -- source register 1 address bit 2

  constant ctrl_rf_rs1_adr3_c   : natural :=  4; -- source register 1 address bit 3

  constant ctrl_rf_rs1_adr4_c   : natural :=  5; -- source register 1 address bit 4

  constant ctrl_rf_rs2_adr0_c   : natural :=  6; -- source register 2 address bit 0

  constant ctrl_rf_rs2_adr1_c   : natural :=  7; -- source register 2 address bit 1

  constant ctrl_rf_rs2_adr2_c   : natural :=  8; -- source register 2 address bit 2

  constant ctrl_rf_rs2_adr3_c   : natural :=  9; -- source register 2 address bit 3

  constant ctrl_rf_rs2_adr4_c   : natural := 10; -- source register 2 address bit 4

  constant ctrl_rf_rd_adr0_c    : natural := 11; -- destination register address bit 0

  constant ctrl_rf_rd_adr1_c    : natural := 12; -- destination register address bit 1

  constant ctrl_rf_rd_adr2_c    : natural := 13; -- destination register address bit 2

  constant ctrl_rf_rd_adr3_c    : natural := 14; -- destination register address bit 3

  constant ctrl_rf_rd_adr4_c    : natural := 15; -- destination register address bit 4

  constant ctrl_rf_wb_en_c      : natural := 16; -- write back enable

  constant ctrl_rf_r0_we_c      : natural := 17; -- force write access and force rd=r0

  -- alu --

  constant ctrl_alu_arith_c     : natural := 18; -- ALU arithmetic command

  constant ctrl_alu_logic0_c    : natural := 19; -- ALU logic command bit 0

  constant ctrl_alu_logic1_c    : natural := 20; -- ALU logic command bit 1

  constant ctrl_alu_func0_c     : natural := 21; -- ALU function select command bit 0

  constant ctrl_alu_func1_c     : natural := 22; -- ALU function select command bit 1

  constant ctrl_alu_addsub_c    : natural := 23; -- 0=ADD, 1=SUB

  constant ctrl_alu_opa_mux_c   : natural := 24; -- operand A select (0=rs1, 1=PC)

  constant ctrl_alu_opb_mux_c   : natural := 25; -- operand B select (0=rs2, 1=IMM)

  constant ctrl_alu_unsigned_c  : natural := 26; -- is unsigned ALU operation

  constant ctrl_alu_shift_dir_c : natural := 27; -- shift direction (0=left, 1=right)

  constant ctrl_alu_shift_ar_c  : natural := 28; -- is arithmetic shift

  -- bus interface --

  constant ctrl_bus_size_lsb_c  : natural := 29; -- transfer size lsb (00=byte, 01=half-word)

  constant ctrl_bus_size_msb_c  : natural := 30; -- transfer size msb (10=word, 11=?)

  constant ctrl_bus_rd_c        : natural := 31; -- read data request

  constant ctrl_bus_wr_c        : natural := 32; -- write data request

  constant ctrl_bus_if_c        : natural := 33; -- instruction fetch request

  constant ctrl_bus_mo_we_c     : natural := 34; -- memory address and data output register write enable

  constant ctrl_bus_mi_we_c     : natural := 35; -- memory data input register write enable

  constant ctrl_bus_unsigned_c  : natural := 36; -- is unsigned load

  constant ctrl_bus_ierr_ack_c  : natural := 37; -- acknowledge instruction fetch bus exceptions

  constant ctrl_bus_derr_ack_c  : natural := 38; -- acknowledge data access bus exceptions

  constant ctrl_bus_fence_c     : natural := 39; -- executed fence operation

  constant ctrl_bus_fencei_c    : natural := 40; -- executed fencei operation

  constant ctrl_bus_lock_c      : natural := 41; -- make atomic/exclusive access lock

  constant ctrl_bus_de_lock_c   : natural := 42; -- remove atomic/exclusive access 

  constant ctrl_bus_ch_lock_c   : natural := 43; -- evaluate atomic/exclusive lock (SC operation)

  -- co-processors --

  constant ctrl_cp_id_lsb_c     : natural := 44; -- cp select ID lsb

  constant ctrl_cp_id_hsb_c     : natural := 45; -- cp select ID

  constant ctrl_cp_id_msb_c     : natural := 46; -- cp select ID msb

  -- instruction's control blocks (used by cpu co-processors) --

  constant ctrl_ir_funct3_0_c   : natural := 47; -- funct3 bit 0

  constant ctrl_ir_funct3_1_c   : natural := 48; -- funct3 bit 1

  constant ctrl_ir_funct3_2_c   : natural := 49; -- funct3 bit 2

  constant ctrl_ir_funct12_0_c  : natural := 50; -- funct12 bit 0

  constant ctrl_ir_funct12_1_c  : natural := 51; -- funct12 bit 1

  constant ctrl_ir_funct12_2_c  : natural := 52; -- funct12 bit 2

  constant ctrl_ir_funct12_3_c  : natural := 53; -- funct12 bit 3

  constant ctrl_ir_funct12_4_c  : natural := 54; -- funct12 bit 4

  constant ctrl_ir_funct12_5_c  : natural := 55; -- funct12 bit 5

  constant ctrl_ir_funct12_6_c  : natural := 56; -- funct12 bit 6

  constant ctrl_ir_funct12_7_c  : natural := 57; -- funct12 bit 7

  constant ctrl_ir_funct12_8_c  : natural := 58; -- funct12 bit 8

  constant ctrl_ir_funct12_9_c  : natural := 59; -- funct12 bit 9

  constant ctrl_ir_funct12_10_c : natural := 60; -- funct12 bit 10

  constant ctrl_ir_funct12_11_c : natural := 61; -- funct12 bit 11

  constant ctrl_ir_opcode7_0_c  : natural := 62; -- opcode7 bit 0

  constant ctrl_ir_opcode7_1_c  : natural := 63; -- opcode7 bit 1

  constant ctrl_ir_opcode7_2_c  : natural := 64; -- opcode7 bit 2

  constant ctrl_ir_opcode7_3_c  : natural := 65; -- opcode7 bit 3

  constant ctrl_ir_opcode7_4_c  : natural := 66; -- opcode7 bit 4

  constant ctrl_ir_opcode7_5_c  : natural := 67; -- opcode7 bit 5

  constant ctrl_ir_opcode7_6_c  : natural := 68; -- opcode7 bit 6

  -- CPU status --

  constant ctrl_priv_lvl_lsb_c  : natural := 69; -- privilege level lsb

  constant ctrl_priv_lvl_msb_c  : natural := 70; -- privilege level msb

  constant ctrl_sleep_c         : natural := 71; -- set when CPU is in sleep mode

  constant ctrl_trap_c          : natural := 72; -- set when CPU is entering trap execution

  constant ctrl_debug_running_c : natural := 73; -- CPU is in debug mode when set

  -- control bus size --

  constant ctrl_width_c         : natural := 74; -- control bus size

  -- Comparator Bus -------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  constant cmp_equal_c : natural := 0;

  constant cmp_less_c  : natural := 1; -- for signed and unsigned comparisons

  -- RISC-V Opcode Layout -------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  constant instr_opcode_lsb_c  : natural :=  0; -- opcode bit 0

  constant instr_opcode_msb_c  : natural :=  6; -- opcode bit 6

  constant instr_rd_lsb_c      : natural :=  7; -- destination register address bit 0

  constant instr_rd_msb_c      : natural := 11; -- destination register address bit 4

  constant instr_funct3_lsb_c  : natural := 12; -- funct3 bit 0

  constant instr_funct3_msb_c  : natural := 14; -- funct3 bit 2

  constant instr_rs1_lsb_c     : natural := 15; -- source register 1 address bit 0

  constant instr_rs1_msb_c     : natural := 19; -- source register 1 address bit 4

  constant instr_rs2_lsb_c     : natural := 20; -- source register 2 address bit 0

  constant instr_rs2_msb_c     : natural := 24; -- source register 2 address bit 4

  constant instr_funct7_lsb_c  : natural := 25; -- funct7 bit 0

  constant instr_funct7_msb_c  : natural := 31; -- funct7 bit 6

  constant instr_funct12_lsb_c : natural := 20; -- funct12 bit 0

  constant instr_funct12_msb_c : natural := 31; -- funct12 bit 11

  constant instr_imm12_lsb_c   : natural := 20; -- immediate12 bit 0

  constant instr_imm12_msb_c   : natural := 31; -- immediate12 bit 11

  constant instr_imm20_lsb_c   : natural := 12; -- immediate20 bit 0

  constant instr_imm20_msb_c   : natural := 31; -- immediate20 bit 21

  constant instr_csr_id_lsb_c  : natural := 20; -- csr select bit 0

  constant instr_csr_id_msb_c  : natural := 31; -- csr select bit 11

  constant instr_funct5_lsb_c  : natural := 27; -- funct5 select bit 0

  constant instr_funct5_msb_c  : natural := 31; -- funct5 select bit 4

  -- RISC-V Opcodes -------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- alu --

  constant opcode_lui_c    : std_ulogic_vector(6 downto 0) := "0110111"; -- load upper immediate

  constant opcode_auipc_c  : std_ulogic_vector(6 downto 0) := "0010111"; -- add upper immediate to PC

  constant opcode_alui_c   : std_ulogic_vector(6 downto 0) := "0010011"; -- ALU operation with immediate (operation via funct3 and funct7)

  constant opcode_alu_c    : std_ulogic_vector(6 downto 0) := "0110011"; -- ALU operation (operation via funct3 and funct7)

  -- control flow --

  constant opcode_jal_c    : std_ulogic_vector(6 downto 0) := "1101111"; -- jump and link

  constant opcode_jalr_c   : std_ulogic_vector(6 downto 0) := "1100111"; -- jump and link with register

  constant opcode_branch_c : std_ulogic_vector(6 downto 0) := "1100011"; -- branch (condition set via funct3)

  -- memory access --

  constant opcode_load_c   : std_ulogic_vector(6 downto 0) := "0000011"; -- load (data type via funct3)

  constant opcode_store_c  : std_ulogic_vector(6 downto 0) := "0100011"; -- store (data type via funct3)

  -- system/csr --

  constant opcode_fence_c  : std_ulogic_vector(6 downto 0) := "0001111"; -- fence / fence.i

  constant opcode_syscsr_c : std_ulogic_vector(6 downto 0) := "1110011"; -- system/csr access (type via funct3)

  -- atomic memory access (A) --

  constant opcode_atomic_c : std_ulogic_vector(6 downto 0) := "0101111"; -- atomic operations (A extension)

  -- floating point operations (Zfinx-only) (F/D/H/Q) --

  constant opcode_fop_c    : std_ulogic_vector(6 downto 0) := "1010011"; -- dual/single opearand instruction

  -- RISC-V Funct3 --------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- control flow --

  constant funct3_beq_c    : std_ulogic_vector(2 downto 0) := "000"; -- branch if equal

  constant funct3_bne_c    : std_ulogic_vector(2 downto 0) := "001"; -- branch if not equal

  constant funct3_blt_c    : std_ulogic_vector(2 downto 0) := "100"; -- branch if less than

  constant funct3_bge_c    : std_ulogic_vector(2 downto 0) := "101"; -- branch if greater than or equal

  constant funct3_bltu_c   : std_ulogic_vector(2 downto 0) := "110"; -- branch if less than (unsigned)

  constant funct3_bgeu_c   : std_ulogic_vector(2 downto 0) := "111"; -- branch if greater than or equal (unsigned)

  -- memory access --

  constant funct3_lb_c     : std_ulogic_vector(2 downto 0) := "000"; -- load byte

  constant funct3_lh_c     : std_ulogic_vector(2 downto 0) := "001"; -- load half word

  constant funct3_lw_c     : std_ulogic_vector(2 downto 0) := "010"; -- load word

  constant funct3_lbu_c    : std_ulogic_vector(2 downto 0) := "100"; -- load byte (unsigned)

  constant funct3_lhu_c    : std_ulogic_vector(2 downto 0) := "101"; -- load half word (unsigned)

  constant funct3_sb_c     : std_ulogic_vector(2 downto 0) := "000"; -- store byte

  constant funct3_sh_c     : std_ulogic_vector(2 downto 0) := "001"; -- store half word

  constant funct3_sw_c     : std_ulogic_vector(2 downto 0) := "010"; -- store word

  -- alu --

  constant funct3_subadd_c : std_ulogic_vector(2 downto 0) := "000"; -- sub/add via funct7

  constant funct3_sll_c    : std_ulogic_vector(2 downto 0) := "001"; -- shift logical left

  constant funct3_slt_c    : std_ulogic_vector(2 downto 0) := "010"; -- set on less

  constant funct3_sltu_c   : std_ulogic_vector(2 downto 0) := "011"; -- set on less unsigned

  constant funct3_xor_c    : std_ulogic_vector(2 downto 0) := "100"; -- xor

  constant funct3_sr_c     : std_ulogic_vector(2 downto 0) := "101"; -- shift right via funct7

  constant funct3_or_c     : std_ulogic_vector(2 downto 0) := "110"; -- or

  constant funct3_and_c    : std_ulogic_vector(2 downto 0) := "111"; -- and

  -- system/csr --

  constant funct3_env_c    : std_ulogic_vector(2 downto 0) := "000"; -- ecall, ebreak, mret, wfi, ...

  constant funct3_csrrw_c  : std_ulogic_vector(2 downto 0) := "001"; -- atomic r/w

  constant funct3_csrrs_c  : std_ulogic_vector(2 downto 0) := "010"; -- atomic read & set bit

  constant funct3_csrrc_c  : std_ulogic_vector(2 downto 0) := "011"; -- atomic read & clear bit

  constant funct3_csrrwi_c : std_ulogic_vector(2 downto 0) := "101"; -- atomic r/w immediate

  constant funct3_csrrsi_c : std_ulogic_vector(2 downto 0) := "110"; -- atomic read & set bit immediate

  constant funct3_csrrci_c : std_ulogic_vector(2 downto 0) := "111"; -- atomic read & clear bit immediate

  -- fence --

  constant funct3_fence_c  : std_ulogic_vector(2 downto 0) := "000"; -- fence - order IO/memory access (->NOP)

  constant funct3_fencei_c : std_ulogic_vector(2 downto 0) := "001"; -- fencei - instructon stream sync

  -- RISC-V Funct12 -------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- system --

  constant funct12_ecall_c  : std_ulogic_vector(11 downto 0) := x"000"; -- ECALL

  constant funct12_ebreak_c : std_ulogic_vector(11 downto 0) := x"001"; -- EBREAK

  constant funct12_mret_c   : std_ulogic_vector(11 downto 0) := x"302"; -- MRET

  constant funct12_wfi_c    : std_ulogic_vector(11 downto 0) := x"105"; -- WFI

  constant funct12_dret_c   : std_ulogic_vector(11 downto 0) := x"7b2"; -- DRET

  -- RISC-V Funct5 --------------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- atomic operations --

  constant funct5_a_lr_c : std_ulogic_vector(4 downto 0) := "00010"; -- LR

  constant funct5_a_sc_c : std_ulogic_vector(4 downto 0) := "00011"; -- SC

  -- RISC-V Floating-Point Stuff ------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- formats --

  constant float_single_c : std_ulogic_vector(1 downto 0) := "00"; -- single-precision (32-bit)

  constant float_double_c : std_ulogic_vector(1 downto 0) := "01"; -- double-precision (64-bit)

  constant float_half_c   : std_ulogic_vector(1 downto 0) := "10"; -- half-precision (16-bit)

  constant float_quad_c   : std_ulogic_vector(1 downto 0) := "11"; -- quad-precision (128-bit)

  -- number class flags --

  constant fp_class_neg_inf_c    : natural := 0; -- negative infinity

  constant fp_class_neg_norm_c   : natural := 1; -- negative normal number

  constant fp_class_neg_denorm_c : natural := 2; -- negative subnormal number

  constant fp_class_neg_zero_c   : natural := 3; -- negative zero

  constant fp_class_pos_zero_c   : natural := 4; -- positive zero

  constant fp_class_pos_denorm_c : natural := 5; -- positive subnormal number

  constant fp_class_pos_norm_c   : natural := 6; -- positive normal number

  constant fp_class_pos_inf_c    : natural := 7; -- positive infinity

  constant fp_class_snan_c       : natural := 8; -- signaling NaN (sNaN)

  constant fp_class_qnan_c       : natural := 9; -- quiet NaN (qNaN)

  -- exception flags --

  constant fp_exc_nv_c : natural := 0; -- invalid operation

  constant fp_exc_dz_c : natural := 1; -- divide by zero

  constant fp_exc_of_c : natural := 2; -- overflow

  constant fp_exc_uf_c : natural := 3; -- underflow

  constant fp_exc_nx_c : natural := 4; -- inexact

  -- special values (single-precision) --

  constant fp_single_qnan_c     : std_ulogic_vector(31 downto 0) := x"7fc00000"; -- quiet NaN

  constant fp_single_snan_c     : std_ulogic_vector(31 downto 0) := x"7fa00000"; -- signaling NaN

  constant fp_single_pos_inf_c  : std_ulogic_vector(31 downto 0) := x"7f800000"; -- positive infinity

  constant fp_single_neg_inf_c  : std_ulogic_vector(31 downto 0) := x"ff800000"; -- negative infinity

  constant fp_single_pos_zero_c : std_ulogic_vector(31 downto 0) := x"00000000"; -- positive zero

  constant fp_single_neg_zero_c : std_ulogic_vector(31 downto 0) := x"80000000"; -- negative zero

  -- RISC-V CSR Addresses -------------------------------------------------------------------

  -- -------------------------------------------------------------------------------------------

  -- <<< standard read/write CSRs >>> --

  -- user floating-point CSRs --

  constant csr_class_float_c    : std_ulogic_vector(07 downto 0) := x"00"; -- floating point

  constant csr_fflags_c         : std_ulogic_vector(11 downto 0) := x"001";

  constant csr_frm_c            : std_ulogic_vector(11 downto 0) := x"002";

  constant csr_fcsr_c           : std_ulogic_vector(11 downto 0) := x"003";

  -- machine trap setup --

  constant csr_class_setup_c    : std_ulogic_vector(07 downto 0) := x"30"; -- trap setup

  constant csr_mstatus_c        : std_ulogic_vector(11 downto 0) := x"300";

  constant csr_misa_c           : std_ulogic_vector(11 downto 0) := x"301";

  constant csr_mie_c            : std_ulogic_vector(11 downto 0) := x"304";