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[/] [neorv32/] [trunk/] [rtl/] [core/] [neorv32_wishbone.vhd] - Blame information for rev 56

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1 2 zero_gravi
-- #################################################################################################
2
-- # << NEORV32 - External Bus Interface (WISHBONE) >>                                             #
3
-- # ********************************************************************************************* #
4 41 zero_gravi
-- # The interface provides registers for all outgoing and for all incoming signals. If the host   #
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-- # cancels an activetransfer, the Wishbone arbiter still waits some time for the bus system to   #
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-- # ACK/ERR the transfer before the arbiter forces termination.                                   #
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-- #                                                                                               #
8 39 zero_gravi
-- # Even when all processor-internal memories and IO devices are disabled, the EXTERNAL address   #
9
-- # space ENDS at address 0xffff0000 (begin of internal BOOTROM address space).                   #
10 41 zero_gravi
-- #                                                                                               #
11 39 zero_gravi
-- # All bus accesses from the CPU, which do not target the internal IO region / the internal      #
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-- # bootlloader / the internal instruction or data memories (if implemented), are delegated via   #
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-- # this Wishbone gateway to the external bus interface. Accessed peripherals can have a response #
14 41 zero_gravi
-- # latency of up to BUS_TIMEOUT - 2 cycles.                                                      #
15
-- #                                                                                               #
16 35 zero_gravi
-- # This interface supports classic/standard Wishbone transactions (WB_PIPELINED_MODE = false)    #
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-- # and also pipelined transactions (WB_PIPELINED_MODE = true).                                   #
18 2 zero_gravi
-- # ********************************************************************************************* #
19
-- # BSD 3-Clause License                                                                          #
20
-- #                                                                                               #
21 44 zero_gravi
-- # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     #
22 2 zero_gravi
-- #                                                                                               #
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-- # Redistribution and use in source and binary forms, with or without modification, are          #
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-- # permitted provided that the following conditions are met:                                     #
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-- #                                                                                               #
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-- # 1. Redistributions of source code must retain the above copyright notice, this list of        #
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-- #    conditions and the following disclaimer.                                                   #
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-- #                                                                                               #
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-- # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
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-- #    conditions and the following disclaimer in the documentation and/or other materials        #
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-- #    provided with the distribution.                                                            #
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-- #                                                                                               #
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-- # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
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-- #    endorse or promote products derived from this software without specific prior written      #
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-- #    permission.                                                                                #
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-- #                                                                                               #
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-- # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
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-- # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
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-- # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
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-- # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
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-- # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
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-- # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
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-- # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
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-- # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
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-- # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
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-- # ********************************************************************************************* #
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-- # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
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-- #################################################################################################
49
 
50
library ieee;
51
use ieee.std_logic_1164.all;
52
use ieee.numeric_std.all;
53
 
54
library neorv32;
55
use neorv32.neorv32_package.all;
56
 
57
entity neorv32_wishbone is
58
  generic (
59 39 zero_gravi
    WB_PIPELINED_MODE : boolean := false;  -- false: classic/standard wishbone mode, true: pipelined wishbone mode
60 23 zero_gravi
    -- Internal instruction memory --
61 44 zero_gravi
    MEM_INT_IMEM_EN   : boolean := true;   -- implement processor-internal instruction memory
62 35 zero_gravi
    MEM_INT_IMEM_SIZE : natural := 8*1024; -- size of processor-internal instruction memory in bytes
63 23 zero_gravi
    -- Internal data memory --
64 44 zero_gravi
    MEM_INT_DMEM_EN   : boolean := true;   -- implement processor-internal data memory
65 41 zero_gravi
    MEM_INT_DMEM_SIZE : natural := 4*1024; -- size of processor-internal data memory in bytes
66
    -- Bus Timeout --
67
    BUS_TIMEOUT       : natural := 63      -- cycles after an UNACKNOWLEDGED bus access triggers a bus fault exception
68 2 zero_gravi
  );
69
  port (
70
    -- global control --
71 53 zero_gravi
    clk_i    : in  std_ulogic; -- global clock line
72
    rstn_i   : in  std_ulogic; -- global reset line, low-active
73 2 zero_gravi
    -- host access --
74 53 zero_gravi
    src_i    : in  std_ulogic; -- access type (0: data, 1:instruction)
75
    addr_i   : in  std_ulogic_vector(31 downto 0); -- address
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    rden_i   : in  std_ulogic; -- read enable
77
    wren_i   : in  std_ulogic; -- write enable
78
    ben_i    : in  std_ulogic_vector(03 downto 0); -- byte write enable
79
    data_i   : in  std_ulogic_vector(31 downto 0); -- data in
80
    data_o   : out std_ulogic_vector(31 downto 0); -- data out
81
    cancel_i : in  std_ulogic; -- cancel current bus transaction
82
    excl_i   : in  std_ulogic; -- exclusive access request
83
    excl_o   : out std_ulogic; -- state of exclusiv access (set if failed)
84
    ack_o    : out std_ulogic; -- transfer acknowledge
85
    err_o    : out std_ulogic; -- transfer error
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    priv_i   : in  std_ulogic_vector(01 downto 0); -- current CPU privilege level
87 2 zero_gravi
    -- wishbone interface --
88 53 zero_gravi
    wb_tag_o : out std_ulogic_vector(03 downto 0); -- request tag
89
    wb_adr_o : out std_ulogic_vector(31 downto 0); -- address
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    wb_dat_i : in  std_ulogic_vector(31 downto 0); -- read data
91
    wb_dat_o : out std_ulogic_vector(31 downto 0); -- write data
92
    wb_we_o  : out std_ulogic; -- read/write
93
    wb_sel_o : out std_ulogic_vector(03 downto 0); -- byte enable
94
    wb_stb_o : out std_ulogic; -- strobe
95
    wb_cyc_o : out std_ulogic; -- valid cycle
96
    wb_tag_i : in  std_ulogic; -- response tag
97
    wb_ack_i : in  std_ulogic; -- transfer acknowledge
98
    wb_err_i : in  std_ulogic  -- transfer error
99 2 zero_gravi
  );
100
end neorv32_wishbone;
101
 
102
architecture neorv32_wishbone_rtl of neorv32_wishbone is
103
 
104 35 zero_gravi
  -- constants --
105 41 zero_gravi
  constant xbus_timeout_c : natural := BUS_TIMEOUT/4;
106 35 zero_gravi
 
107 2 zero_gravi
  -- access control --
108 39 zero_gravi
  signal int_imem_acc : std_ulogic;
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  signal int_dmem_acc : std_ulogic;
110
  signal int_boot_acc : std_ulogic;
111
  signal xbus_access  : std_ulogic;
112 2 zero_gravi
 
113 35 zero_gravi
  -- bus arbiter
114 38 zero_gravi
  type ctrl_state_t is (IDLE, BUSY, CANCELED, RESYNC);
115 35 zero_gravi
  type ctrl_t is record
116 39 zero_gravi
    state   : ctrl_state_t;
117
    we      : std_ulogic;
118
    rd_req  : std_ulogic;
119
    wr_req  : std_ulogic;
120
    adr     : std_ulogic_vector(31 downto 0);
121
    wdat    : std_ulogic_vector(31 downto 0);
122
    rdat    : std_ulogic_vector(31 downto 0);
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    sel     : std_ulogic_vector(3 downto 0);
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    ack     : std_ulogic;
125
    err     : std_ulogic;
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    timeout : std_ulogic_vector(index_size_f(xbus_timeout_c)-1 downto 0);
127
    src     : std_ulogic;
128 53 zero_gravi
    excl    : std_ulogic;
129
    exclr   : std_ulogic; -- response
130 39 zero_gravi
    priv    : std_ulogic_vector(1 downto 0);
131 35 zero_gravi
  end record;
132 36 zero_gravi
  signal ctrl    : ctrl_t;
133
  signal stb_int : std_ulogic;
134
  signal cyc_int : std_ulogic;
135 2 zero_gravi
 
136
begin
137
 
138 35 zero_gravi
  -- Sanity Checks --------------------------------------------------------------------------
139 2 zero_gravi
  -- -------------------------------------------------------------------------------------------
140 39 zero_gravi
  -- max bus timeout latency lower than recommended --
141 41 zero_gravi
  assert not (BUS_TIMEOUT <= 32) report "NEORV32 PROCESSOR CONFIG WARNING: Bus timeout should be >32 when using external bus interface." severity warning;
142 39 zero_gravi
  -- external memory iterface protocol + max timeout latency notifier (warning) --
143 41 zero_gravi
  assert not (wb_pipe_mode_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: Implementing external memory interface using STANDARD Wishbone protocol." severity note;
144
  assert not (wb_pipe_mode_c = true) report "NEORV32 PROCESSOR CONFIG NOTE! Implementing external memory interface using PIEPLINED Wishbone protocol." severity note;
145 40 zero_gravi
  -- endianness --
146
  assert not (xbus_big_endian_c = false) report "NEORV32 PROCESSOR CONFIG NOTE: Using LITTLE-ENDIAN byte order for external memory interface." severity note;
147
  assert not (xbus_big_endian_c = true)  report "NEORV32 PROCESSOR CONFIG NOTE: Using BIG-ENDIAN byte order for external memory interface." severity note;
148 2 zero_gravi
 
149
 
150
  -- Access Control -------------------------------------------------------------------------
151
  -- -------------------------------------------------------------------------------------------
152 39 zero_gravi
  -- access to processor-internal IMEM or DMEM? --
153 44 zero_gravi
  int_imem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_IMEM_SIZE)) = imem_base_c(31 downto index_size_f(MEM_INT_IMEM_SIZE))) and (MEM_INT_IMEM_EN = true) else '0';
154
  int_dmem_acc <= '1' when (addr_i(31 downto index_size_f(MEM_INT_DMEM_SIZE)) = dmem_base_c(31 downto index_size_f(MEM_INT_DMEM_SIZE))) and (MEM_INT_DMEM_EN = true) else '0';
155 39 zero_gravi
  -- access to processor-internal BOOTROM or IO devices? --
156
  int_boot_acc <= '1' when (addr_i(31 downto 16) = boot_rom_base_c(31 downto 16)) else '0'; -- hacky!
157 2 zero_gravi
  -- actual external bus access? --
158 39 zero_gravi
  xbus_access <= (not int_imem_acc) and (not int_dmem_acc) and (not int_boot_acc);
159 2 zero_gravi
 
160
  -- Bus Arbiter -----------------------------------------------------------------------------
161
  -- -------------------------------------------------------------------------------------------
162
  bus_arbiter: process(rstn_i, clk_i)
163
  begin
164
    if (rstn_i = '0') then
165 39 zero_gravi
      ctrl.state   <= IDLE;
166
      ctrl.we      <= '0';
167
      ctrl.rd_req  <= '0';
168
      ctrl.wr_req  <= '0';
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      ctrl.adr     <= (others => '0');
170
      ctrl.wdat    <= (others => '0');
171
      ctrl.rdat    <= (others => '0');
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      ctrl.sel     <= (others => '0');
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      ctrl.timeout <= (others => '0');
174
      ctrl.ack     <= '0';
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      ctrl.err     <= '0';
176
      ctrl.src     <= '0';
177 53 zero_gravi
      ctrl.excl    <= '0';
178
      ctrl.exclr   <= '0';
179 39 zero_gravi
      ctrl.priv    <= "00";
180 2 zero_gravi
    elsif rising_edge(clk_i) then
181 35 zero_gravi
      -- defaults --
182 39 zero_gravi
      ctrl.rdat    <= (others => '0');
183
      ctrl.ack     <= '0';
184
      ctrl.err     <= '0';
185 53 zero_gravi
      ctrl.exclr   <= '0';
186 39 zero_gravi
      ctrl.timeout <= std_ulogic_vector(to_unsigned(xbus_timeout_c, index_size_f(xbus_timeout_c)));
187 2 zero_gravi
 
188 35 zero_gravi
      -- state machine --
189
      case ctrl.state is
190 2 zero_gravi
 
191 35 zero_gravi
        when IDLE => -- waiting for host request
192
        -- ------------------------------------------------------------
193
          ctrl.rd_req <= '0';
194
          ctrl.wr_req <= '0';
195
          -- buffer all outgoing signals --
196 56 zero_gravi
          ctrl.we  <= wren_i or ctrl.wr_req;
197
          ctrl.adr <= addr_i;
198 40 zero_gravi
          if (xbus_big_endian_c = true) then -- endianness conversion
199
            ctrl.wdat <= data_i;
200
            ctrl.sel  <= ben_i;
201
          else
202
            ctrl.wdat <= bswap32_f(data_i);
203
            ctrl.sel  <= bit_rev_f(ben_i);
204
          end if;
205 36 zero_gravi
          ctrl.src  <= src_i;
206 53 zero_gravi
          ctrl.excl <= excl_i;
207 36 zero_gravi
          ctrl.priv <= priv_i;
208 39 zero_gravi
          -- valid new or buffered read/write request --
209 56 zero_gravi
          if ((xbus_access and (wren_i or ctrl.wr_req or rden_i or ctrl.rd_req) and (not cancel_i)) = '1') then
210 35 zero_gravi
            ctrl.state <= BUSY;
211
          end if;
212 2 zero_gravi
 
213 35 zero_gravi
        when BUSY => -- transfer in progress
214
        -- ------------------------------------------------------------
215 53 zero_gravi
          ctrl.rdat  <= wb_dat_i;
216
          ctrl.exclr <= wb_tag_i; -- set if exclusive access success
217 35 zero_gravi
          if (cancel_i = '1') then -- transfer canceled by host
218
            ctrl.state <= CANCELED;
219
          elsif (wb_err_i = '1') then -- abnormal bus termination
220
            ctrl.err   <= '1';
221
            ctrl.state <= CANCELED;
222
          elsif (wb_ack_i = '1') then -- normal bus termination
223
            ctrl.ack   <= '1';
224
            ctrl.state <= IDLE;
225
          end if;
226 2 zero_gravi
 
227 38 zero_gravi
        when CANCELED => -- wait for cycle to be completed either by peripheral or by timeout (ignore result of transfer)
228 35 zero_gravi
        -- ------------------------------------------------------------
229
          ctrl.wr_req <= ctrl.wr_req or wren_i; -- buffer new request
230
          ctrl.rd_req <= ctrl.rd_req or rden_i; -- buffer new request
231
          -- wait for bus.peripheral to ACK transfer (as "aborted" but still somehow "completed")
232
          -- or wait for a timeout and force termination
233
          ctrl.timeout <= std_ulogic_vector(unsigned(ctrl.timeout) - 1); -- timeout counter
234
          if (wb_ack_i = '1') or (or_all_f(ctrl.timeout) = '0') then
235 38 zero_gravi
            ctrl.state <= RESYNC;
236
          end if;
237
 
238
        when RESYNC => -- make sure transfer is done!
239
        -- ------------------------------------------------------------
240 56 zero_gravi
          ctrl.wr_req <= ctrl.wr_req or wren_i; -- buffer new request
241
          ctrl.rd_req <= ctrl.rd_req or rden_i; -- buffer new request
242 38 zero_gravi
          if (wb_ack_i = '0') then
243 35 zero_gravi
            ctrl.state <= IDLE;
244
          end if;
245 2 zero_gravi
 
246 35 zero_gravi
        when others => -- undefined
247
        -- ------------------------------------------------------------
248
          ctrl.state <= IDLE;
249 2 zero_gravi
 
250 35 zero_gravi
      end case;
251
    end if;
252
  end process bus_arbiter;
253 23 zero_gravi
 
254 35 zero_gravi
  -- host access --
255 40 zero_gravi
  data_o <= ctrl.rdat when (xbus_big_endian_c = true) else bswap32_f(ctrl.rdat); -- endianness conversion
256 39 zero_gravi
  ack_o  <= ctrl.ack;
257
  err_o  <= ctrl.err;
258 53 zero_gravi
  excl_o <= ctrl.exclr;
259 2 zero_gravi
 
260 35 zero_gravi
  -- wishbone interface --
261 36 zero_gravi
  wb_tag_o(0) <= '1' when (ctrl.priv = priv_mode_m_c) else '0'; -- privileged access when in machine mode
262 39 zero_gravi
  wb_tag_o(1) <= '0'; -- 0 = secure, 1 = non-secure
263
  wb_tag_o(2) <= ctrl.src; -- 0 = data access, 1 = instruction access
264 53 zero_gravi
  wb_tag_o(3) <= ctrl.excl; -- 1 = exclusive access request
265 36 zero_gravi
 
266 39 zero_gravi
  wb_adr_o  <= ctrl.adr;
267
  wb_dat_o  <= ctrl.wdat;
268
  wb_we_o   <= ctrl.we;
269
  wb_sel_o  <= ctrl.sel;
270
  wb_stb_o  <= stb_int when (WB_PIPELINED_MODE = true) else cyc_int;
271
  wb_cyc_o  <= cyc_int;
272 2 zero_gravi
 
273 39 zero_gravi
  stb_int <= '1' when (ctrl.state = BUSY) else '0';
274
  cyc_int <= '0' when (ctrl.state = IDLE) or (ctrl.state = RESYNC) else '1';
275 2 zero_gravi
 
276 35 zero_gravi
 
277 2 zero_gravi
end neorv32_wishbone_rtl;

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