URL https://opencores.org/ocsvn/neorv32/neorv32/trunk

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [sw/] [common/] [crt0.S] - Blame information for rev 59

Go to most recent revision | Details | Compare with Previous | View Log


/* ################################################################################################# */
/* # << NEORV32 - crt0.S - Start-Up Code >>                                                        # */
/* # ********************************************************************************************* # */
/* # BSD 3-Clause License                                                                          # */
/* #                                                                                               # */
/* # Copyright (c) 2021, Stephan Nolting. All rights reserved.                                     # */
/* #                                                                                               # */
/* # Redistribution and use in source and binary forms, with or without modification, are          # */
/* # permitted provided that the following conditions are met:                                     # */
/* #                                                                                               # */
/* # 1. Redistributions of source code must retain the above copyright notice, this list of        # */
/* #    conditions and the following disclaimer.                                                   # */
/* #                                                                                               # */
/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     # */
/* #    conditions and the following disclaimer in the documentation and/or other materials        # */
/* #    provided with the distribution.                                                            # */
/* #                                                                                               # */
/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  # */
/* #    endorse or promote products derived from this software without specific prior written      # */
/* #    permission.                                                                                # */
/* #                                                                                               # */
/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   # */
/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               # */
/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    # */
/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     # */
/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */
/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    # */
/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     # */
/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  # */
/* # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            # */
/* # ********************************************************************************************* # */
/* # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting # */
/* ################################################################################################# */
 
.file   "crt0.S"
.section .text.boot
.balign 4
.global _start
 
 
_start:
.cfi_startproc
.cfi_undefined ra
 
  nop
 
// *********************************************************
// Clear integer register file (lower half, assume E extension)
// *********************************************************
__crt0_reg_file_clear:
//addi  x0, x0, 0 // hardwired to zero
  addi  x1, x0, 0
  addi  x2, x0, 0
  addi  x3, x0, 0
  addi  x4, x0, 0
  addi  x5, x0, 0
  addi  x6, x0, 0
  addi  x7, x0, 0
//addi  x8, x0, 0
//addi  x9, x0, 0
//addi x10, x0, 0
//addi x11, x0, 0
//addi x12, x0, 0
//addi x13, x0, 0
  addi x14, x0, 0
  addi x15, x0, 0
 
 
// *********************************************************
// Setup pointers using linker script symbols
// *********************************************************
__crt0_pointer_init:
.option push
.option norelax
  la    sp, __crt0_stack_begin
  andi  sp, sp, 0xfffffffc // make sure this is aligned
  addi  fp, sp, 0          // frame pointer = stack pointer
  la gp, __global_pointer$ // global pointer
.option pop
 
 
// *********************************************************
// Setup CPU core CSRs (some of them DO NOT have a dedicated reset and need to be explicitly initialized)
// *********************************************************
__crt0_cpu_csr_init:
 
  // set address of first-level exception handler
  la   x10, __crt0_dummy_trap_handler
  csrw mtvec,  x10
  csrw mepc,   x10
  csrw mtval,  zero
  csrw mcause, zero
 
  // no global IRQ enable (is also done by hardware)
  csrw mstatus, zero
 
  // absolutely no interrupts, thanks
  csrw mie, zero
 
  // no access from less-privileged modes to counter CSRs
  csrw mcounteren, zero
 
  // stop all counters except for [m]cycle[h] and [m]instret[h]
  li   x11, ~5
  csrw 0x320, x11 // mcountinhibit (literal address for lagacy toolchain compatibility)
 
  // clear cycle counters
  csrw mcycle,  zero
  csrw mcycleh, zero
 
  // clear instruction counters
  csrw minstret,  zero
  csrw minstreth, zero
 
#if defined(__riscv_flen) && (__riscv_flen != 0)
  // clear floating-point CSR (rounding mode & exception flags)
  csrw fcsr, zero
#endif
 
 
// *********************************************************
// Clear integer register file (upper half, if no E extension)
// *********************************************************
#ifndef __riscv_32e
// DO NOT DO THIS if compiling bootloader (to save some program space)
#ifndef make_bootloader
  addi x16, x0, 0
  addi x17, x0, 0
  addi x18, x0, 0
  addi x19, x0, 0
  addi x20, x0, 0
  addi x21, x0, 0
  addi x22, x0, 0
  addi x23, x0, 0
  addi x24, x0, 0
  addi x25, x0, 0
  addi x26, x0, 0
  addi x27, x0, 0
  addi x28, x0, 0
  addi x29, x0, 0
  addi x30, x0, 0
  addi x31, x0, 0
#endif
#endif
 
 
// *********************************************************
// Reset/deactivate IO/peripheral devices
// Devices, that are not implemented, will cause a store access fault
// which is captured but actually ignored due to the dummy handler.
// *********************************************************
__crt0_reset_io:
  la x8, __ctr0_io_space_begin // start of processor-internal IO region
  la x9, __ctr0_io_space_end   // end of processor-internal IO region
 
__crt0_reset_io_loop:
  sw   zero, 0(x8)
  addi x8,   x8, 4
  bne  x8,   x9, __crt0_reset_io_loop
 
 
// *********************************************************
// Clear .bss section (byte-wise) using linker script symbols
// *********************************************************
__crt0_clear_bss:
  la x11, __crt0_bss_start
  la x12, __crt0_bss_end
 
__crt0_clear_bss_loop:
  bge  x11, x12, __crt0_clear_bss_loop_end
  sb   zero, 0(x11)
  addi x11, x11, 1
  j    __crt0_clear_bss_loop
 
__crt0_clear_bss_loop_end:
 
 
// *********************************************************
// Copy initialized .data section from ROM to RAM (byte-wise) using linker script symbols
// *********************************************************
__crt0_copy_data:
  la x11, __crt0_copy_data_src_begin  // start of data area (copy source)
  la x12, __crt0_copy_data_dst_begin  // start of data area (copy destination)
  la x13, __crt0_copy_data_dst_end    // last address of destination data area
 
__crt0_copy_data_loop:
  bge  x12, x13,  __crt0_copy_data_loop_end
  lb   x14, 0(x11)
  sb   x14, 0(x12)
  addi x11, x11, 1
  addi x12, x12, 1
  j    __crt0_copy_data_loop
 
__crt0_copy_data_loop_end:
 
 
// *********************************************************
// Call main function
// *********************************************************
__crt0_main_entry:
 
  // setup arguments for calling main
  addi x10, zero, 0 // argc = 0
  addi x11, zero, 0 // argv = 0
 
  // call actual app's main function
  jal ra, main
 
 
// *********************************************************
// Go to endless sleep mode if main returns
// *********************************************************
__crt0_this_is_the_end:
  csrrci zero, mstatus, 8 // mstatus: disable global IRQs (MIE)
__crt0_this_is_the_end_my_friend:
  wfi
  j __crt0_this_is_the_end_my_friend
 
 
// *********************************************************
// dummy trap handler (for exceptions & IRQs)
// tries to move on to next instruction
// *********************************************************
.global __crt0_dummy_trap_handler
.balign 4
__crt0_dummy_trap_handler:
 
  addi  sp, sp, -8
  sw      x8, 0(sp)
  sw      x9, 4(sp)
 
  csrr  x8, mcause
  blt   x8, zero, __crt0_dummy_trap_handler_irq  // skip mepc modification if interrupt
 
  csrr  x8, mepc
 
// is compressed instruction?
__crt0_dummy_trap_handler_exc_c_check:
  lh    x9, 0(x8)   // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception
  andi  x9, x9, 3   // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)
 
  addi  x8, x8, +2  // only this for compressed instructions
  csrw  mepc, x8    // set return address when compressed instruction
 
  addi  x8, zero, 3
  bne   x8, x9, __crt0_dummy_trap_handler_irq // jump if compressed instruction
 
// is uncompressed instruction
__crt0_dummy_trap_handler_exc_uncrompressed:
  csrr  x8, mepc
  addi  x8, x8, +2  // add another 2 (making +4) for uncompressed instructions
  csrw  mepc, x8
 
__crt0_dummy_trap_handler_irq:
 
  lw    x8, 0(sp)
  lw    x9, 4(sp)
  addi  sp, sp, +8
 
  mret
 
.cfi_endproc
.end

Line No.	Rev	Author	Line
1	2	zero_gravi	`/* ################################################################################################# */`
2	21	zero_gravi	`/* # << NEORV32 - crt0.S - Start-Up Code >> # */`
3	2	zero_gravi	`/* # ********************************************************************************************* # */`
4			`/* # BSD 3-Clause License # */`
5			`/* # # */`
6	53	zero_gravi	`/* # Copyright (c) 2021, Stephan Nolting. All rights reserved. # */`
7	2	zero_gravi	`/* # # */`
8			`/* # Redistribution and use in source and binary forms, with or without modification, are # */`
9			`/* # permitted provided that the following conditions are met: # */`
10			`/* # # */`
11			`/* # 1. Redistributions of source code must retain the above copyright notice, this list of # */`
12			`/* # conditions and the following disclaimer. # */`
13			`/* # # */`
14			`/* # 2. Redistributions in binary form must reproduce the above copyright notice, this list of # */`
15			`/* # conditions and the following disclaimer in the documentation and/or other materials # */`
16			`/* # provided with the distribution. # */`
17			`/* # # */`
18			`/* # 3. Neither the name of the copyright holder nor the names of its contributors may be used to # */`
19			`/* # endorse or promote products derived from this software without specific prior written # */`
20			`/* # permission. # */`
21			`/* # # */`
22			`/* # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS # */`
23			`/* # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF # */`
24			`/* # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE # */`
25			`/* # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, # */`
26			`/* # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE # */`
27			`/* # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED # */`
28			`/* # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING # */`
29			`/* # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED # */`
30			`/* # OF THE POSSIBILITY OF SUCH DAMAGE. # */`
31			`/* # ********************************************************************************************* # */`
32			`/* # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting # */`
33			`/* ################################################################################################# */`
34
35	21	zero_gravi	`.file "crt0.S"`
36			`.section .text.boot`
37			`.balign 4`
38			`.global _start`
39	2	zero_gravi
40
41			`_start:`
42	21	zero_gravi	`.cfi_startproc`
43			`.cfi_undefined ra`
44	2	zero_gravi
45	59	zero_gravi	`nop`
46
47	2	zero_gravi	`// *********************************************************`
48	52	zero_gravi	`// Clear integer register file (lower half, assume E extension)`
49	2	zero_gravi	`// *********************************************************`
50			`__crt0_reg_file_clear:`
51	32	zero_gravi	`//addi x0, x0, 0 // hardwired to zero`
52			`addi x1, x0, 0`
53			`addi x2, x0, 0`
54			`addi x3, x0, 0`
55			`addi x4, x0, 0`
56			`addi x5, x0, 0`
57			`addi x6, x0, 0`
58			`addi x7, x0, 0`
59	58	zero_gravi	`//addi x8, x0, 0`
60			`//addi x9, x0, 0`
61	32	zero_gravi	`//addi x10, x0, 0`
62			`//addi x11, x0, 0`
63			`//addi x12, x0, 0`
64			`//addi x13, x0, 0`
65			`addi x14, x0, 0`
66			`addi x15, x0, 0`
67	2	zero_gravi
68
69			`// *********************************************************`
70	56	zero_gravi	`// Setup pointers using linker script symbols`
71	32	zero_gravi	`// *********************************************************`
72	56	zero_gravi	`__crt0_pointer_init:`
73			`.option push`
74			`.option norelax`
75			`la sp, __crt0_stack_begin`
76			`andi sp, sp, 0xfffffffc // make sure this is aligned`
77			`addi fp, sp, 0 // frame pointer = stack pointer`
78			`la gp, __global_pointer$ // global pointer`
79			`.option pop`
80	52	zero_gravi
81
82			`// *********************************************************`
83	56	zero_gravi	`// Setup CPU core CSRs (some of them DO NOT have a dedicated reset and need to be explicitly initialized)`
84			`// *********************************************************`
85			`__crt0_cpu_csr_init:`
86
87			`// set address of first-level exception handler`
88			`la x10, __crt0_dummy_trap_handler`
89			`csrw mtvec, x10`
90			`csrw mepc, x10`
91			`csrw mtval, zero`
92			`csrw mcause, zero`
93
94			`// no global IRQ enable (is also done by hardware)`
95			`csrw mstatus, zero`
96
97			`// absolutely no interrupts, thanks`
98			`csrw mie, zero`
99
100			`// no access from less-privileged modes to counter CSRs`
101			`csrw mcounteren, zero`
102
103			`// stop all counters except for [m]cycle[h] and [m]instret[h]`
104			`li x11, ~5`
105	58	zero_gravi	`csrw 0x320, x11 // mcountinhibit (literal address for lagacy toolchain compatibility)`
106	56	zero_gravi
107			`// clear cycle counters`
108	58	zero_gravi	`csrw mcycle, zero`
109			`csrw mcycleh, zero`
110	56	zero_gravi
111			`// clear instruction counters`
112			`csrw minstret, zero`
113			`csrw minstreth, zero`
114
115			`#if defined(__riscv_flen) && (__riscv_flen != 0)`
116			`// clear floating-point CSR (rounding mode & exception flags)`
117			`csrw fcsr, zero`
118			`#endif`
119
120
121			`// *********************************************************`
122	52	zero_gravi	`// Clear integer register file (upper half, if no E extension)`
123			`// *********************************************************`
124	32	zero_gravi	`#ifndef __riscv_32e`
125	52	zero_gravi	`// DO NOT DO THIS if compiling bootloader (to save some program space)`
126	32	zero_gravi	`#ifndef make_bootloader`
127			`addi x16, x0, 0`
128			`addi x17, x0, 0`
129			`addi x18, x0, 0`
130			`addi x19, x0, 0`
131			`addi x20, x0, 0`
132			`addi x21, x0, 0`
133			`addi x22, x0, 0`
134			`addi x23, x0, 0`
135			`addi x24, x0, 0`
136			`addi x25, x0, 0`
137			`addi x26, x0, 0`
138			`addi x27, x0, 0`
139			`addi x28, x0, 0`
140			`addi x29, x0, 0`
141			`addi x30, x0, 0`
142			`addi x31, x0, 0`
143			`#endif`
144			`#endif`
145
146
147			`// *********************************************************`
148	2	zero_gravi	`// Reset/deactivate IO/peripheral devices`
149			`// Devices, that are not implemented, will cause a store access fault`
150			`// which is captured but actually ignored due to the dummy handler.`
151			`// *********************************************************`
152			`__crt0_reset_io:`
153	58	zero_gravi	`la x8, __ctr0_io_space_begin // start of processor-internal IO region`
154			`la x9, __ctr0_io_space_end // end of processor-internal IO region`
155	2	zero_gravi
156			`__crt0_reset_io_loop:`
157	58	zero_gravi	`sw zero, 0(x8)`
158			`addi x8, x8, 4`
159			`bne x8, x9, __crt0_reset_io_loop`
160	2	zero_gravi
161
162			`// *********************************************************`
163	23	zero_gravi	`// Clear .bss section (byte-wise) using linker script symbols`
164	2	zero_gravi	`// *********************************************************`
165			`__crt0_clear_bss:`
166			`la x11, __crt0_bss_start`
167			`la x12, __crt0_bss_end`
168
169			`__crt0_clear_bss_loop:`
170			`bge x11, x12, __crt0_clear_bss_loop_end`
171			`sb zero, 0(x11)`
172			`addi x11, x11, 1`
173			`j __crt0_clear_bss_loop`
174
175			`__crt0_clear_bss_loop_end:`
176
177
178			`// *********************************************************`
179	23	zero_gravi	`// Copy initialized .data section from ROM to RAM (byte-wise) using linker script symbols`
180	2	zero_gravi	`// *********************************************************`
181			`__crt0_copy_data:`
182			`la x11, __crt0_copy_data_src_begin // start of data area (copy source)`
183			`la x12, __crt0_copy_data_dst_begin // start of data area (copy destination)`
184			`la x13, __crt0_copy_data_dst_end // last address of destination data area`
185
186			`__crt0_copy_data_loop:`
187			`bge x12, x13, __crt0_copy_data_loop_end`
188			`lb x14, 0(x11)`
189			`sb x14, 0(x12)`
190			`addi x11, x11, 1`
191			`addi x12, x12, 1`
192			`j __crt0_copy_data_loop`
193
194			`__crt0_copy_data_loop_end:`
195
196
197			`// *********************************************************`
198	39	zero_gravi	`// Call main function`
199	2	zero_gravi	`// *********************************************************`
200			`__crt0_main_entry:`
201
202	39	zero_gravi	`// setup arguments for calling main`
203	2	zero_gravi	`addi x10, zero, 0 // argc = 0`
204			`addi x11, zero, 0 // argv = 0`
205
206	40	zero_gravi	`// call actual app's main function`
207	2	zero_gravi	`jal ra, main`
208
209
210			`// *********************************************************`
211			`// Go to endless sleep mode if main returns`
212			`// *********************************************************`
213			`__crt0_this_is_the_end:`
214	11	zero_gravi	`csrrci zero, mstatus, 8 // mstatus: disable global IRQs (MIE)`
215	59	zero_gravi	`__crt0_this_is_the_end_my_friend:`
216	2	zero_gravi	`wfi`
217	59	zero_gravi	`j __crt0_this_is_the_end_my_friend`
218	2	zero_gravi
219
220			`// *********************************************************`
221	14	zero_gravi	`// dummy trap handler (for exceptions & IRQs)`
222			`// tries to move on to next instruction`
223	2	zero_gravi	`// *********************************************************`
224	21	zero_gravi	`.global __crt0_dummy_trap_handler`
225			`.balign 4`
226	14	zero_gravi	`__crt0_dummy_trap_handler:`
227	2	zero_gravi
228	14	zero_gravi	`addi sp, sp, -8`
229			`sw x8, 0(sp)`
230			`sw x9, 4(sp)`
231	2	zero_gravi
232	14	zero_gravi	`csrr x8, mcause`
233			`blt x8, zero, __crt0_dummy_trap_handler_irq // skip mepc modification if interrupt`
234	2	zero_gravi
235	14	zero_gravi	`csrr x8, mepc`
236	2	zero_gravi
237	14	zero_gravi	`// is compressed instruction?`
238	23	zero_gravi	`__crt0_dummy_trap_handler_exc_c_check:`
239	14	zero_gravi	`lh x9, 0(x8) // get compressed instruction or lower 16 bits of uncompressed instruction that caused exception`
240			`andi x9, x9, 3 // mask: isolate lowest 2 opcode bits (= 11 for uncompressed instructions)`
241	2	zero_gravi
242	14	zero_gravi	`addi x8, x8, +2 // only this for compressed instructions`
243			`csrw mepc, x8 // set return address when compressed instruction`
244	2	zero_gravi
245	14	zero_gravi	`addi x8, zero, 3`
246			`bne x8, x9, __crt0_dummy_trap_handler_irq // jump if compressed instruction`
247	7	zero_gravi
248	14	zero_gravi	`// is uncompressed instruction`
249	23	zero_gravi	`__crt0_dummy_trap_handler_exc_uncrompressed:`
250	14	zero_gravi	`csrr x8, mepc`
251			`addi x8, x8, +2 // add another 2 (making +4) for uncompressed instructions`
252			`csrw mepc, x8`
253	2	zero_gravi
254	14	zero_gravi	`__crt0_dummy_trap_handler_irq:`
255	2	zero_gravi
256	53	zero_gravi	`lw x8, 0(sp)`
257			`lw x9, 4(sp)`
258	23	zero_gravi	`addi sp, sp, +8`
259	2	zero_gravi
260			`mret`
261
262	21	zero_gravi	`.cfi_endproc`
263			`.end`

Browse

Tools

Subversion Repositories neorv32

[/] [neorv32/] [trunk/] [sw/] [common/] [crt0.S] - Blame information for rev 59