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// #################################################################################################
// # << NEORV32: neorv32_intrinsics.h - Helper functions/macros for (custom) "intrinsics" >>       #
// # ********************************************************************************************* #
// # BSD 3-Clause License                                                                          #
// #                                                                                               #
// # Copyright (c) 2022, Stephan Nolting. All rights reserved.                                     #
// #                                                                                               #
// # Redistribution and use in source and binary forms, with or without modification, are          #
// # permitted provided that the following conditions are met:                                     #
// #                                                                                               #
// # 1. Redistributions of source code must retain the above copyright notice, this list of        #
// #    conditions and the following disclaimer.                                                   #
// #                                                                                               #
// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of     #
// #    conditions and the following disclaimer in the documentation and/or other materials        #
// #    provided with the distribution.                                                            #
// #                                                                                               #
// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to  #
// #    endorse or promote products derived from this software without specific prior written      #
// #    permission.                                                                                #
// #                                                                                               #
// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS   #
// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF               #
// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE    #
// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,     #
// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #
// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED    #
// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING     #
// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED  #
// # OF THE POSSIBILITY OF SUCH DAMAGE.                                                            #
// # ********************************************************************************************* #
// # The NEORV32 Processor - https://github.com/stnolting/neorv32              (c) Stephan Nolting #
// #################################################################################################
 
 
/**********************************************************************//**
 * @file neorv32_intrinsics.h
 * @brief Helper functions and macros for custom "intrinsics" / instructions.
 **************************************************************************/
 
#ifndef neorv32_intrinsics_h
#define neorv32_intrinsics_h
 
 
// ****************************************************************************************************************************
// Custom Instruction Intrinsics
// Derived from https://github.com/google/CFU-Playground/blob/dfe5c2b75a4540dab62baef1b12fd03bfa78425e/third_party/SaxonSoc/riscv.h
// Original license header:
//
//   From https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/software/standalone/driver/riscv.h
//
//   Copyright (c) 2019 SaxonSoc contributors
//
//   MIT License: https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/LICENSE
//
// LICENSE:
//  MIT License
//  
//  Copyright (c) 2019 SaxonSoc contributors
//  
//  Permission is hereby granted, free of charge, to any person obtaining a copy
//  of this software and associated documentation files (the "Software"), to deal
//  in the Software without restriction, including without limitation the rights
//  to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
//  copies of the Software, and to permit persons to whom the Software is
//  furnished to do so, subject to the following conditions:
//  
//  The above copyright notice and this permission notice shall be included in all
//  copies or substantial portions of the Software.
//  
//  THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
//  IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
//  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
//  AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
//  LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
//  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
//  SOFTWARE.
// ****************************************************************************************************************************
 
/**********************************************************************//**
 * @name Custom Instruction Intrinsics
 * @note Copied from https://github.com/google/CFU-Playground/blob/dfe5c2b75a4540dab62baef1b12fd03bfa78425e/third_party/SaxonSoc/riscv.h
 *       Original license header:
 * // From https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/software/standalone/driver/riscv.h
 * //
 * // Copyright (c) 2019 SaxonSoc contributors
 * //
 * // MIT License: https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/LICENSE
 **************************************************************************/
/**@{*/
asm(".set regnum_x0  ,  0");
asm(".set regnum_x1  ,  1");
asm(".set regnum_x2  ,  2");
asm(".set regnum_x3  ,  3");
asm(".set regnum_x4  ,  4");
asm(".set regnum_x5  ,  5");
asm(".set regnum_x6  ,  6");
asm(".set regnum_x7  ,  7");
asm(".set regnum_x8  ,  8");
asm(".set regnum_x9  ,  9");
asm(".set regnum_x10 , 10");
asm(".set regnum_x11 , 11");
asm(".set regnum_x12 , 12");
asm(".set regnum_x13 , 13");
asm(".set regnum_x14 , 14");
asm(".set regnum_x15 , 15");
asm(".set regnum_x16 , 16");
asm(".set regnum_x17 , 17");
asm(".set regnum_x18 , 18");
asm(".set regnum_x19 , 19");
asm(".set regnum_x20 , 20");
asm(".set regnum_x21 , 21");
asm(".set regnum_x22 , 22");
asm(".set regnum_x23 , 23");
asm(".set regnum_x24 , 24");
asm(".set regnum_x25 , 25");
asm(".set regnum_x26 , 26");
asm(".set regnum_x27 , 27");
asm(".set regnum_x28 , 28");
asm(".set regnum_x29 , 29");
asm(".set regnum_x30 , 30");
asm(".set regnum_x31 , 31");
 
asm(".set regnum_zero,  0");
asm(".set regnum_ra  ,  1");
asm(".set regnum_sp  ,  2");
asm(".set regnum_gp  ,  3");
asm(".set regnum_tp  ,  4");
asm(".set regnum_t0  ,  5");
asm(".set regnum_t1  ,  6");
asm(".set regnum_t2  ,  7");
asm(".set regnum_s0  ,  8");
asm(".set regnum_s1  ,  9");
asm(".set regnum_a0  , 10");
asm(".set regnum_a1  , 11");
asm(".set regnum_a2  , 12");
asm(".set regnum_a3  , 13");
asm(".set regnum_a4  , 14");
asm(".set regnum_a5  , 15");
asm(".set regnum_a6  , 16");
asm(".set regnum_a7  , 17");
asm(".set regnum_s2  , 18");
asm(".set regnum_s3  , 19");
asm(".set regnum_s4  , 20");
asm(".set regnum_s5  , 21");
asm(".set regnum_s6  , 22");
asm(".set regnum_s7  , 23");
asm(".set regnum_s8  , 24");
asm(".set regnum_s9  , 25");
asm(".set regnum_s10 , 26");
asm(".set regnum_s11 , 27");
asm(".set regnum_t3  , 28");
asm(".set regnum_t4  , 29");
asm(".set regnum_t5  , 30");
asm(".set regnum_t6  , 31");
 
/** Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1) */
asm(".set RISCV_OPCODE_CUSTOM0 , 0b0001011");
asm(".set RISCV_OPCODE_CUSTOM1 , 0b0101011");
/**@}*/
 
 
/**********************************************************************//**
 * @name Custom instruction R1-type format
 **************************************************************************/
#define CUSTOM_INSTR_R1_TYPE(funct7, funct5, rs1, funct3, opcode) \
({                                                                \
    register uint32_t __return;                                   \
    asm volatile (                                                \
      ""                                                          \
      : [output] "=r" (__return)                                  \
      : [input_i] "r" (rs1)                                       \
    );                                                            \
    asm volatile(                                                 \
      ".word (                                                    \
        (((" #funct7 ") & 0x7f) << 25) |                          \
        (((" #funct5 ") & 0x1f) << 20) |                          \
        ((( regnum_%1 ) & 0x1f) << 15) |                          \
        (((" #funct3 ") & 0x07) << 12) |                          \
        ((( regnum_%0 ) & 0x1f) <<  7) |                          \
        (((" #opcode ") & 0x7f) <<  0)                            \
      );"                                                         \
      : [rd] "=r" (__return)                                      \
      : "r" (rs1)                                                 \
    );                                                            \
    __return;                                                     \
})
 
 
/**********************************************************************//**
 * @name Custom instruction R2-type format
 **************************************************************************/
#define CUSTOM_INSTR_R2_TYPE(funct7, rs2, rs1, funct3, opcode) \
({                                                             \
    register uint32_t __return;                                \
    asm volatile (                                             \
      ""                                                       \
      : [output] "=r" (__return)                               \
      : [input_i] "r" (rs1),                                   \
        [input_j] "r" (rs2)                                    \
    );                                                         \
    asm volatile (                                             \
      ".word (                                                 \
        (((" #funct7 ") & 0x7f) << 25) |                       \
        ((( regnum_%2 ) & 0x1f) << 20) |                       \
        ((( regnum_%1 ) & 0x1f) << 15) |                       \
        (((" #funct3 ") & 0x07) << 12) |                       \
        ((( regnum_%0 ) & 0x1f) <<  7) |                       \
        (((" #opcode ") & 0x7f) <<  0)                         \
      );"                                                      \
      : [rd] "=r" (__return)                                   \
      : "r" (rs1),                                             \
        "r" (rs2)                                              \
    );                                                         \
    __return;                                                  \
})
 
 
/**********************************************************************//**
 * @name Custom instruction R3-type format
 **************************************************************************/
#define CUSTOM_INSTR_R3_TYPE(rs3, rs2, rs1, funct3, opcode) \
({                                                          \
    register uint32_t __return;                             \
    asm volatile (                                          \
      ""                                                    \
      : [output] "=r" (__return)                            \
      : [input_i] "r" (rs1),                                \
        [input_j] "r" (rs2),                                \
        [input_k] "r" (rs3)                                 \
    );                                                      \
    asm volatile (                                          \
      ".word (                                              \
        ((( regnum_%3 ) & 0x1f) << 25) |                    \
        ((( regnum_%2 ) & 0x1f) << 20) |                    \
        ((( regnum_%1 ) & 0x1f) << 15) |                    \
        (((" #funct3 ") & 0x07) << 12) |                    \
        ((( regnum_%0 ) & 0x1f) <<  7) |                    \
        (((" #opcode ") & 0x7f) <<  0)                      \
      );"                                                   \
      : [rd] "=r" (__return)                                \
      : "r" (rs1),                                          \
        "r" (rs2),                                          \
        "r" (rs3)                                           \
    );                                                      \
    __return;                                               \
})
 
 
/**********************************************************************//**
 * @name Custom instruction I-type format
 **************************************************************************/
#define CUSTOM_INSTR_I_TYPE(imm12, rs1, funct3, opcode) \
({                                                      \
    register uint32_t __return;                         \
    asm volatile (                                      \
      ""                                                \
      : [output] "=r" (__return)                        \
      : [input_i] "r" (rs1)                             \
    );                                                  \
    asm volatile (                                      \
      ".word (                                          \
        (((" #imm12 ")  & 0xfff) << 20) |               \
        ((( regnum_%1 ) &  0x1f) << 15) |               \
        (((" #funct3 ") &  0x07) << 12) |               \
        ((( regnum_%0 ) &  0x1f) <<  7) |               \
        (((" #opcode ") &  0x7f) <<  0)                 \
      );"                                               \
      : [rd] "=r" (__return)                            \
      : "r" (rs1)                                       \
    );                                                  \
    __return;                                           \
})
 
 
#endif // neorv32_intrinsics_h

Line No.	Rev	Author	Line
1	54	zero_gravi	`// #################################################################################################`
2	55	zero_gravi	`// # << NEORV32: neorv32_intrinsics.h - Helper functions/macros for (custom) "intrinsics" >> #`
3	54	zero_gravi	`// # ********************************************************************************************* #`
4			`// # BSD 3-Clause License #`
5			`// # #`
6	71	zero_gravi	`// # Copyright (c) 2022, Stephan Nolting. All rights reserved. #`
7	54	zero_gravi	`// # #`
8			`// # Redistribution and use in source and binary forms, with or without modification, are #`
9			`// # permitted provided that the following conditions are met: #`
10			`// # #`
11			`// # 1. Redistributions of source code must retain the above copyright notice, this list of #`
12			`// # conditions and the following disclaimer. #`
13			`// # #`
14			`// # 2. Redistributions in binary form must reproduce the above copyright notice, this list of #`
15			`// # conditions and the following disclaimer in the documentation and/or other materials #`
16			`// # provided with the distribution. #`
17			`// # #`
18			`// # 3. Neither the name of the copyright holder nor the names of its contributors may be used to #`
19			`// # endorse or promote products derived from this software without specific prior written #`
20			`// # permission. #`
21			`// # #`
22			`// # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS #`
23			`// # OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF #`
24			`// # MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE #`
25			`// # COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, #`
26			`// # EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE #`
27			`// # GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED #`
28			`// # AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING #`
29			`// # NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED #`
30			`// # OF THE POSSIBILITY OF SUCH DAMAGE. #`
31			`// # ********************************************************************************************* #`
32			`// # The NEORV32 Processor - https://github.com/stnolting/neorv32 (c) Stephan Nolting #`
33			`// #################################################################################################`
34
35
36			`/********************************************************************//`
37			`* @file neorv32_intrinsics.h`
38			`* @brief Helper functions and macros for custom "intrinsics" / instructions.`
39			`**************************************************************************/`
40
41			`#ifndef neorv32_intrinsics_h`
42			`#define neorv32_intrinsics_h`
43
44	71	zero_gravi
45			`// ****************************************************************************************************************************`
46			`// Custom Instruction Intrinsics`
47			`// Derived from https://github.com/google/CFU-Playground/blob/dfe5c2b75a4540dab62baef1b12fd03bfa78425e/third_party/SaxonSoc/riscv.h`
48			`// Original license header:`
49			`//`
50			`// From https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/software/standalone/driver/riscv.h`
51			`//`
52			`// Copyright (c) 2019 SaxonSoc contributors`
53			`//`
54			`// MIT License: https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/LICENSE`
55			`//`
56			`// LICENSE:`
57			`// MIT License`
58			`//`
59			`// Copyright (c) 2019 SaxonSoc contributors`
60			`//`
61			`// Permission is hereby granted, free of charge, to any person obtaining a copy`
62			`// of this software and associated documentation files (the "Software"), to deal`
63			`// in the Software without restriction, including without limitation the rights`
64			`// to use, copy, modify, merge, publish, distribute, sublicense, and/or sell`
65			`// copies of the Software, and to permit persons to whom the Software is`
66			`// furnished to do so, subject to the following conditions:`
67			`//`
68			`// The above copyright notice and this permission notice shall be included in all`
69			`// copies or substantial portions of the Software.`
70			`//`
71			`// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR`
72			`// IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,`
73			`// FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE`
74			`// AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER`
75			`// LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,`
76			`// OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE`
77			`// SOFTWARE.`
78			`// ****************************************************************************************************************************`
79
80	54	zero_gravi	`/********************************************************************//`
81	71	zero_gravi	`* @name Custom Instruction Intrinsics`
82			`* @note Copied from https://github.com/google/CFU-Playground/blob/dfe5c2b75a4540dab62baef1b12fd03bfa78425e/third_party/SaxonSoc/riscv.h`
83			`* Original license header:`
84			`* // From https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/software/standalone/driver/riscv.h`
85			`* //`
86			`* // Copyright (c) 2019 SaxonSoc contributors`
87			`* //`
88			`* // MIT License: https://github.com/SpinalHDL/SaxonSoc/blob/dev-0.1/LICENSE`
89	54	zero_gravi	`**************************************************************************/`
90			`/*@{/`
91	71	zero_gravi	`asm(".set regnum_x0 , 0");`
92			`asm(".set regnum_x1 , 1");`
93			`asm(".set regnum_x2 , 2");`
94			`asm(".set regnum_x3 , 3");`
95			`asm(".set regnum_x4 , 4");`
96			`asm(".set regnum_x5 , 5");`
97			`asm(".set regnum_x6 , 6");`
98			`asm(".set regnum_x7 , 7");`
99			`asm(".set regnum_x8 , 8");`
100			`asm(".set regnum_x9 , 9");`
101			`asm(".set regnum_x10 , 10");`
102			`asm(".set regnum_x11 , 11");`
103			`asm(".set regnum_x12 , 12");`
104			`asm(".set regnum_x13 , 13");`
105			`asm(".set regnum_x14 , 14");`
106			`asm(".set regnum_x15 , 15");`
107			`asm(".set regnum_x16 , 16");`
108			`asm(".set regnum_x17 , 17");`
109			`asm(".set regnum_x18 , 18");`
110			`asm(".set regnum_x19 , 19");`
111			`asm(".set regnum_x20 , 20");`
112			`asm(".set regnum_x21 , 21");`
113			`asm(".set regnum_x22 , 22");`
114			`asm(".set regnum_x23 , 23");`
115			`asm(".set regnum_x24 , 24");`
116			`asm(".set regnum_x25 , 25");`
117			`asm(".set regnum_x26 , 26");`
118			`asm(".set regnum_x27 , 27");`
119			`asm(".set regnum_x28 , 28");`
120			`asm(".set regnum_x29 , 29");`
121			`asm(".set regnum_x30 , 30");`
122			`asm(".set regnum_x31 , 31");`
123	54	zero_gravi
124	71	zero_gravi	`asm(".set regnum_zero, 0");`
125			`asm(".set regnum_ra , 1");`
126			`asm(".set regnum_sp , 2");`
127			`asm(".set regnum_gp , 3");`
128			`asm(".set regnum_tp , 4");`
129			`asm(".set regnum_t0 , 5");`
130			`asm(".set regnum_t1 , 6");`
131			`asm(".set regnum_t2 , 7");`
132			`asm(".set regnum_s0 , 8");`
133			`asm(".set regnum_s1 , 9");`
134			`asm(".set regnum_a0 , 10");`
135			`asm(".set regnum_a1 , 11");`
136			`asm(".set regnum_a2 , 12");`
137			`asm(".set regnum_a3 , 13");`
138			`asm(".set regnum_a4 , 14");`
139			`asm(".set regnum_a5 , 15");`
140			`asm(".set regnum_a6 , 16");`
141			`asm(".set regnum_a7 , 17");`
142			`asm(".set regnum_s2 , 18");`
143			`asm(".set regnum_s3 , 19");`
144			`asm(".set regnum_s4 , 20");`
145			`asm(".set regnum_s5 , 21");`
146			`asm(".set regnum_s6 , 22");`
147			`asm(".set regnum_s7 , 23");`
148			`asm(".set regnum_s8 , 24");`
149			`asm(".set regnum_s9 , 25");`
150			`asm(".set regnum_s10 , 26");`
151			`asm(".set regnum_s11 , 27");`
152			`asm(".set regnum_t3 , 28");`
153			`asm(".set regnum_t4 , 29");`
154			`asm(".set regnum_t5 , 30");`
155			`asm(".set regnum_t6 , 31");`
156	72	zero_gravi
157			`/** Official RISC-V opcodes for custom extensions (CUSTOM0, CUSTOM1) */`
158			`asm(".set RISCV_OPCODE_CUSTOM0 , 0b0001011");`
159			`asm(".set RISCV_OPCODE_CUSTOM1 , 0b0101011");`
160	71	zero_gravi	`/*@}/`
161	54	zero_gravi
162
163	71	zero_gravi	`/********************************************************************//`
164			`* @name Custom instruction R1-type format`
165			`**************************************************************************/`
166			`#define CUSTOM_INSTR_R1_TYPE(funct7, funct5, rs1, funct3, opcode) \`
167			`({ \`
168			`register uint32_t __return; \`
169			`asm volatile ( \`
170			`"" \`
171			`: [output] "=r" (__return) \`
172			`: [input_i] "r" (rs1) \`
173			`); \`
174			`asm volatile( \`
175			`".word ( \`
176			`(((" #funct7 ") & 0x7f) << 25) \| \`
177			`(((" #funct5 ") & 0x1f) << 20) \| \`
178			`((( regnum_%1 ) & 0x1f) << 15) \| \`
179			`(((" #funct3 ") & 0x07) << 12) \| \`
180			`((( regnum_%0 ) & 0x1f) << 7) \| \`
181			`(((" #opcode ") & 0x7f) << 0) \`
182			`);" \`
183			`: [rd] "=r" (__return) \`
184			`: "r" (rs1) \`
185			`); \`
186			`__return; \`
187			`})`
188	54	zero_gravi
189
190	71	zero_gravi	`/********************************************************************//`
191			`* @name Custom instruction R2-type format`
192			`**************************************************************************/`
193			`#define CUSTOM_INSTR_R2_TYPE(funct7, rs2, rs1, funct3, opcode) \`
194			`({ \`
195			`register uint32_t __return; \`
196			`asm volatile ( \`
197			`"" \`
198			`: [output] "=r" (__return) \`
199	72	zero_gravi	`: [input_i] "r" (rs1), \`
200			`[input_j] "r" (rs2) \`
201	71	zero_gravi	`); \`
202			`asm volatile ( \`
203			`".word ( \`
204			`(((" #funct7 ") & 0x7f) << 25) \| \`
205			`((( regnum_%2 ) & 0x1f) << 20) \| \`
206			`((( regnum_%1 ) & 0x1f) << 15) \| \`
207			`(((" #funct3 ") & 0x07) << 12) \| \`
208			`((( regnum_%0 ) & 0x1f) << 7) \| \`
209			`(((" #opcode ") & 0x7f) << 0) \`
210			`);" \`
211			`: [rd] "=r" (__return) \`
212	72	zero_gravi	`: "r" (rs1), \`
213			`"r" (rs2) \`
214	71	zero_gravi	`); \`
215			`__return; \`
216			`})`
217	55	zero_gravi
218	54	zero_gravi
219	71	zero_gravi	`/********************************************************************//`
220			`* @name Custom instruction R3-type format`
221			`**************************************************************************/`
222			`#define CUSTOM_INSTR_R3_TYPE(rs3, rs2, rs1, funct3, opcode) \`
223			`({ \`
224			`register uint32_t __return; \`
225			`asm volatile ( \`
226			`"" \`
227			`: [output] "=r" (__return) \`
228	72	zero_gravi	`: [input_i] "r" (rs1), \`
229			`[input_j] "r" (rs2), \`
230			`[input_k] "r" (rs3) \`
231	71	zero_gravi	`); \`
232			`asm volatile ( \`
233			`".word ( \`
234			`((( regnum_%3 ) & 0x1f) << 25) \| \`
235			`((( regnum_%2 ) & 0x1f) << 20) \| \`
236			`((( regnum_%1 ) & 0x1f) << 15) \| \`
237			`(((" #funct3 ") & 0x07) << 12) \| \`
238			`((( regnum_%0 ) & 0x1f) << 7) \| \`
239			`(((" #opcode ") & 0x7f) << 0) \`
240			`);" \`
241			`: [rd] "=r" (__return) \`
242	72	zero_gravi	`: "r" (rs1), \`
243			`"r" (rs2), \`
244			`"r" (rs3) \`
245	71	zero_gravi	`); \`
246			`__return; \`
247			`})`
248	54	zero_gravi
249	55	zero_gravi
250	71	zero_gravi	`/********************************************************************//`
251			`* @name Custom instruction I-type format`
252			`**************************************************************************/`
253			`#define CUSTOM_INSTR_I_TYPE(imm12, rs1, funct3, opcode) \`
254			`({ \`
255			`register uint32_t __return; \`
256			`asm volatile ( \`
257			`"" \`
258			`: [output] "=r" (__return) \`
259			`: [input_i] "r" (rs1) \`
260			`); \`
261			`asm volatile ( \`
262			`".word ( \`
263			`(((" #imm12 ") & 0xfff) << 20) \| \`
264			`((( regnum_%1 ) & 0x1f) << 15) \| \`
265			`(((" #funct3 ") & 0x07) << 12) \| \`
266			`((( regnum_%0 ) & 0x1f) << 7) \| \`
267			`(((" #opcode ") & 0x7f) << 0) \`
268			`);" \`
269			`: [rd] "=r" (__return) \`
270			`: "r" (rs1) \`
271			`); \`
272			`__return; \`
273			`})`
274	54	zero_gravi
275	71	zero_gravi
276	54	zero_gravi	`#endif // neorv32_intrinsics_h`

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