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[/] [numbert_sort_device/] [trunk/] [boards/] [DE0/] [DE0_VGA.v] - Blame information for rev 2

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// --------------------------------------------------------------------
// Copyright (c) 2009 by Terasic Technologies Inc. 
// --------------------------------------------------------------------
//
// Permission:
//
//   Terasic grants permission to use and modify this code for use
//   in synthesis for all Terasic Development Boards and Altera Development 
//   Kits made by Terasic.  Other use of this code, including the selling 
//   ,duplication, or modification of any portion is strictly prohibited.
//
// Disclaimer:
//
//   This VHDL/Verilog or C/C++ source code is intended as a design reference
//   which illustrates how these types of functions can be implemented.
//   It is the user's responsibility to verify their design for
//   consistency and functionality through the use of formal
//   verification methods.  Terasic provides no warranty regarding the use 
//   or functionality of this code.
//
// --------------------------------------------------------------------
//           
//                     Terasic Technologies Inc
//                     356 Fu-Shin E. Rd Sec. 1. JhuBei City,
//                     HsinChu County, Taiwan
//                     302
//
//                     web: http://www.terasic.com/
//                     email: support@terasic.com
//
// --------------------------------------------------------------------
//
// Major Functions:     DE0 VGA
//
// --------------------------------------------------------------------
//
// Revision History :
// --------------------------------------------------------------------
//   Ver  :| Author            :| Mod. Date :| Changes Made:
 
// --------------------------------------------------------------------
 
 
module DE0_VGA
        (
                ////////////////////    Clock Input             ////////////////////     
                CLOCK_50,                                               //      50 MHz
                CLOCK_50_2,                                             //      50 MHz
                ////////////////////    Push Button             ////////////////////
                BUTTON,                                                 //      Pushbutton[2:0]
                ////////////////////    DPDT Switch             ////////////////////
                SW,                                                             //      Toggle Switch[9:0]
                ////////////////////    7-SEG Dispaly   ////////////////////
                HEX0_D,                                                 //      Seven Segment Digit 0
                HEX0_DP,                                                //      Seven Segment Digit DP 0
                HEX1_D,                                                 //      Seven Segment Digit 1
                HEX1_DP,                                                //      Seven Segment Digit DP 1
                HEX2_D,                                                 //      Seven Segment Digit 2
                HEX2_DP,                                                //      Seven Segment Digit DP 2
                HEX3_D,                                                 //      Seven Segment Digit 3
                HEX3_DP,                                                //      Seven Segment Digit DP 3
                ////////////////////////        LED             ////////////////////////
                LEDG,                                                   //      LED Green[9:0]
                ////////////////////////        UART    ////////////////////////
                UART_TXD,                                               //      UART Transmitter
                UART_RXD,                                               //      UART Receiver
                UART_CTS,                                               //      UART Clear To Send
                UART_RTS,                                               //      UART Request To Send
                /////////////////////   SDRAM Interface         ////////////////
                DRAM_DQ,                                                //      SDRAM Data bus 16 Bits
                DRAM_ADDR,                                              //      SDRAM Address bus 13 Bits
                DRAM_LDQM,                                              //      SDRAM Low-byte Data Mask 
                DRAM_UDQM,                                              //      SDRAM High-byte Data Mask
                DRAM_WE_N,                                              //      SDRAM Write Enable
                DRAM_CAS_N,                                             //      SDRAM Column Address Strobe
                DRAM_RAS_N,                                             //      SDRAM Row Address Strobe
                DRAM_CS_N,                                              //      SDRAM Chip Select
                DRAM_BA_0,                                              //      SDRAM Bank Address 0
                DRAM_BA_1,                                              //      SDRAM Bank Address 1
                DRAM_CLK,                                               //      SDRAM Clock
                DRAM_CKE,                                               //      SDRAM Clock Enable
                ////////////////////    Flash Interface         ////////////////
                FL_DQ,                                                  //      FLASH Data bus 15 Bits
                FL_DQ15_AM1,                                    //      FLASH Data bus Bit 15 or Address A-1
                FL_ADDR,                                                //      FLASH Address bus 22 Bits
                FL_WE_N,                                                //      FLASH Write Enable
                FL_RST_N,                                               //      FLASH Reset
                FL_OE_N,                                                //      FLASH Output Enable
                FL_CE_N,                                                //      FLASH Chip Enable
                FL_WP_N,                                                //      FLASH Hardware Write Protect
                FL_BYTE_N,                                              //      FLASH Selects 8/16-bit mode
                FL_RY,                                                  //      FLASH Ready/Busy
                ////////////////////    LCD Module 16X2         ////////////////
                LCD_BLON,                                               //      LCD Back Light ON/OFF
                LCD_RW,                                                 //      LCD Read/Write Select, 0 = Write, 1 = Read
                LCD_EN,                                                 //      LCD Enable
                LCD_RS,                                                 //      LCD Command/Data Select, 0 = Command, 1 = Data
                LCD_DATA,                                               //      LCD Data bus 8 bits
                ////////////////////    SD_Card Interface       ////////////////
                SD_DAT0,                                                //      SD Card Data 0
                SD_DAT3,                                                //      SD Card Data 3
                SD_CMD,                                                 //      SD Card Command Signal
                SD_CLK,                                                 //      SD Card Clock
                SD_WP_N,                                                //      SD Card Write Protect
                ////////////////////    PS2             ////////////////////////////
                PS2_KBDAT,                                              //      PS2 Keyboard Data
                PS2_KBCLK,                                              //      PS2 Keyboard Clock
                PS2_MSDAT,                                              //      PS2 Mouse Data
                PS2_MSCLK,                                              //      PS2 Mouse Clock
                ////////////////////    VGA             ////////////////////////////
                VGA_HS,                                                 //      VGA H_SYNC
                VGA_VS,                                                 //      VGA V_SYNC
                VGA_R,                                                  //      VGA Red[3:0]
                VGA_G,                                                  //      VGA Green[3:0]
                VGA_B,                                                  //      VGA Blue[3:0]
                ////////////////////    GPIO    ////////////////////////////
                GPIO0_CLKIN,                                            //      GPIO Connection 0 Clock In Bus
                GPIO0_CLKOUT,                                   //      GPIO Connection 0 Clock Out Bus
                GPIO0_D,                                                //      GPIO Connection 0 Data Bus
                GPIO1_CLKIN,                                    //      GPIO Connection 1 Clock In Bus
                GPIO1_CLKOUT,                                   //      GPIO Connection 1 Clock Out Bus
                GPIO1_D                                                 //      GPIO Connection 1 Data Bus
        );
 
parameter R_SZ= 128;
 
 
////////////////////////        Clock Input             ////////////////////////
input                   CLOCK_50;                               //      50 MHz
input                   CLOCK_50_2;                             //      50 MHz
////////////////////////        Push Button             ////////////////////////
input   [2:0]    BUTTON;                                 //      Pushbutton[2:0]
////////////////////////        DPDT Switch             ////////////////////////
input   [9:0]    SW;                                             //      Toggle Switch[9:0]
////////////////////////        7-SEG Dispaly   ////////////////////////
output  [6:0]    HEX0_D;                                 //      Seven Segment Digit 0
output                  HEX0_DP;                                //      Seven Segment Digit DP 0
output  [6:0]    HEX1_D;                                 //      Seven Segment Digit 1
output                  HEX1_DP;                                //      Seven Segment Digit DP 1
output  [6:0]    HEX2_D;                                 //      Seven Segment Digit 2
output                  HEX2_DP;                                //      Seven Segment Digit DP 2
output  [6:0]    HEX3_D;                                 //      Seven Segment Digit 3
output                  HEX3_DP;                                //      Seven Segment Digit DP 3
////////////////////////////    LED             ////////////////////////////
output  [9:0]    LEDG;                                   //      LED Green[9:0]
////////////////////////////    UART    ////////////////////////////
output                  UART_TXD;                               //      UART Transmitter
input                   UART_RXD;                               //      UART Receiver
output                  UART_CTS;                               //      UART Clear To Send
input                   UART_RTS;                               //      UART Request To Send
///////////////////////         SDRAM Interface ////////////////////////
inout   [15:0]   DRAM_DQ;                                //      SDRAM Data bus 16 Bits
output  [12:0]   DRAM_ADDR;                              //      SDRAM Address bus 13 Bits
output                  DRAM_LDQM;                              //      SDRAM Low-byte Data Mask
output                  DRAM_UDQM;                              //      SDRAM High-byte Data Mask
output                  DRAM_WE_N;                              //      SDRAM Write Enable
output                  DRAM_CAS_N;                             //      SDRAM Column Address Strobe
output                  DRAM_RAS_N;                             //      SDRAM Row Address Strobe
output                  DRAM_CS_N;                              //      SDRAM Chip Select
output                  DRAM_BA_0;                              //      SDRAM Bank Address 0
output                  DRAM_BA_1;                              //      SDRAM Bank Address 1
output                  DRAM_CLK;                               //      SDRAM Clock
output                  DRAM_CKE;                               //      SDRAM Clock Enable
////////////////////////        Flash Interface ////////////////////////
inout   [14:0]   FL_DQ;                                  //      FLASH Data bus 15 Bits
inout                   FL_DQ15_AM1;                    //      FLASH Data bus Bit 15 or Address A-1
output  [21:0]   FL_ADDR;                                //      FLASH Address bus 22 Bits
output                  FL_WE_N;                                //      FLASH Write Enable
output                  FL_RST_N;                               //      FLASH Reset
output                  FL_OE_N;                                //      FLASH Output Enable
output                  FL_CE_N;                                //      FLASH Chip Enable
output                  FL_WP_N;                                //      FLASH Hardware Write Protect
output                  FL_BYTE_N;                              //      FLASH Selects 8/16-bit mode
input                   FL_RY;                                  //      FLASH Ready/Busy
////////////////////    LCD Module 16X2 ////////////////////////////
inout   [7:0]    LCD_DATA;                               //      LCD Data bus 8 bits
output                  LCD_BLON;                               //      LCD Back Light ON/OFF
output                  LCD_RW;                                 //      LCD Read/Write Select, 0 = Write, 1 = Read
output                  LCD_EN;                                 //      LCD Enable
output                  LCD_RS;                                 //      LCD Command/Data Select, 0 = Command, 1 = Data
////////////////////    SD Card Interface       ////////////////////////
inout                   SD_DAT0;                                //      SD Card Data 0
inout                   SD_DAT3;                                //      SD Card Data 3
inout                   SD_CMD;                                 //      SD Card Command Signal
output                  SD_CLK;                                 //      SD Card Clock
input                   SD_WP_N;                                //      SD Card Write Protect
////////////////////////        PS2             ////////////////////////////////
inout                   PS2_KBDAT;                              //      PS2 Keyboard Data
inout                   PS2_KBCLK;                              //      PS2 Keyboard Clock
inout                   PS2_MSDAT;                              //      PS2 Mouse Data
inout                   PS2_MSCLK;                              //      PS2 Mouse Clock
////////////////////////        VGA                     ////////////////////////////
output                  VGA_HS; //      VGA H_SYNC
output                  VGA_VS; //      VGA V_SYNC
output  [3:0]    VGA_R;                                  //      VGA Red[3:0]
output  [3:0]    VGA_G;                                  //      VGA Green[3:0]
output  [3:0]    VGA_B;                                  //      VGA Blue[3:0]
////////////////////////        GPIO    ////////////////////////////////
input   [1:0]    GPIO0_CLKIN;                    //      GPIO Connection 0 Clock In Bus
output  [1:0]    GPIO0_CLKOUT;                   //      GPIO Connection 0 Clock Out Bus
inout   [31:0]   GPIO0_D;                                //      GPIO Connection 0 Data Bus
input   [1:0]    GPIO1_CLKIN;                    //      GPIO Connection 1 Clock In Bus
output  [1:0]    GPIO1_CLKOUT;                   //      GPIO Connection 1 Clock Out Bus
inout   [31:0]   GPIO1_D;                                //      GPIO Connection 1 Data Bus
 
//=======================================================
//  REG/WIRE declarations
//=======================================================
//      All inout port turn to tri-state
assign                  DRAM_DQ                 =       16'hzzzz;
assign                  FL_DQ                   =       16'hzzzz;
assign                  LCD_DATA                =       8'hzz;
assign                  SD_DAT0                 =       1'hz;
assign                  SD_DAT3                 =       1'hz;
assign                  SD_CMD                  =       1'hz;
assign                  PS2_KBDAT               =       1'hz;
assign                  PS2_KBCLK               =       1'hz;
assign                  PS2_MSDAT               =       1'hz;
assign                  PS2_MSCLK               =       1'hz;
assign                  GPIO0_D                 =       32'hzzzzzzzz;
assign                  GPIO1_D                 =       32'hzzzzzzzz;
 
//assign                        HEX0_D                  =       7'h7F;
assign                  HEX0_DP                 =       ~seg_first;
//assign                        HEX1_D                  =       7'h7F;
assign                  HEX1_DP                 =       ~seg_first;
//assign                        HEX2_D                  =       7'h7F;
assign                  HEX2_DP                 =       ~seg_first;
//assign                        HEX3_D                  =       7'h7F;
assign                  HEX3_DP                 =       ~seg_first;
 
assign                  LEDG                    =       10'h000;
////////////////////////        VGA                     ////////////////////////////
wire                    VGA_CTRL_CLK;
wire    [11:0]   mVGA_X;
wire    [11:0]   mVGA_Y;
wire    [9:0]    mVGA_R;
wire    [9:0]    mVGA_G;
wire    [9:0]    mVGA_B;
 
wire    [9:0]    sVGA_R;
wire    [9:0]    sVGA_G;
wire    [9:0]    sVGA_B;
assign  VGA_R   =       sVGA_R[7:4];
assign  VGA_G   =       sVGA_G[7:4];
assign  VGA_B   =       sVGA_B[7:4];
 
//=======================================================
//  Structural coding
//=======================================================
 
////////////////////////        VGA                     ////////////////////////////
 
 
VGA_CLK         u1_1240x1024
                (       .inclk0(CLOCK_50),
                        .c0(VGA_CTRL_CLK)
                );
                defparam u1_1240x1024.PLL_MUL= 54;
                defparam u1_1240x1024.PLL_DIV= 25;
 
 
VGA_Ctrl        u2_1240x1024
                (       //      Host Side
                        .oCurrent_X(mVGA_X),
                        .oCurrent_Y(mVGA_Y),
                        .iRed(mVGA_R),
                        .iGreen(mVGA_G),
                        .iBlue(mVGA_B),
                        //      VGA Side
                        .oVGA_R(sVGA_R),
                        .oVGA_G(sVGA_G),
                        .oVGA_B(sVGA_B),
                        .oVGA_HS(VGA_HS),
                        .oVGA_VS(VGA_VS),
                        .oVGA_SYNC(),
                        .oVGA_BLANK(),
                        .oVGA_CLOCK(),
                        //      Control Signal
                        .iCLK(VGA_CTRL_CLK),
                        .iRST_N(BUTTON[0]),
                        .les_btn(BUTTON[1])
                );
                defparam        u2_1240x1024.H_FRONT    =       48;
                defparam        u2_1240x1024.H_SYNC     =       112;
                defparam        u2_1240x1024.H_BACK     =       248;
                defparam        u2_1240x1024.H_ACT      =       1280;
                defparam        u2_1240x1024.V_FRONT    =       1;
                defparam        u2_1240x1024.V_SYNC     =       3;
                defparam        u2_1240x1024.V_BACK     =       38;
                defparam        u2_1240x1024.V_ACT      =       1024;
 
wire [63:0] dbg_val;
 
VGA_Pattern #( R_SZ )   u3
                (       //      Read Out Side
                        .oRed(mVGA_R),
                        .oGreen(mVGA_G),
                        .oBlue(mVGA_B),
                        .iVGA_X(mVGA_X),
                        .iVGA_Y(mVGA_Y),
                        .iVGA_CLK(VGA_CTRL_CLK),
                        //      Control Signals
                        .iRST_n(BUTTON[0]),
                        .iColor_SW(SW),
                        .endFrame(VGA_VS),
                        .dbg_val(dbg_val)
                );
 
wire [15:0] indicated_part;
wire seg_first;
 
dbg_7seg dbg_num
                (  .val( dbg_val ),
                        .show_next(BUTTON[1]),
                        .part( indicated_part ),
                        .is_first( seg_first ) );
 
SEG7_LUT_4      u0
                (       .oSEG0(HEX0_D),
                        .oSEG1(HEX1_D),
                        .oSEG2(HEX2_D),
                        .oSEG3(HEX3_D),
                        .iDIG( indicated_part )
                );
 
 
endmodule

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Subversion Repositories numbert_sort_device

[/] [numbert_sort_device/] [trunk/] [boards/] [DE0/] [DE0_VGA.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	leshabiruk	`// --------------------------------------------------------------------`
2			`// Copyright (c) 2009 by Terasic Technologies Inc.`
3			`// --------------------------------------------------------------------`
4			`//`
5			`// Permission:`
6			`//`
7			`// Terasic grants permission to use and modify this code for use`
8			`// in synthesis for all Terasic Development Boards and Altera Development`
9			`// Kits made by Terasic. Other use of this code, including the selling`
10			`// ,duplication, or modification of any portion is strictly prohibited.`
11			`//`
12			`// Disclaimer:`
13			`//`
14			`// This VHDL/Verilog or C/C++ source code is intended as a design reference`
15			`// which illustrates how these types of functions can be implemented.`
16			`// It is the user's responsibility to verify their design for`
17			`// consistency and functionality through the use of formal`
18			`// verification methods. Terasic provides no warranty regarding the use`
19			`// or functionality of this code.`
20			`//`
21			`// --------------------------------------------------------------------`
22			`//`
23			`// Terasic Technologies Inc`
24			`// 356 Fu-Shin E. Rd Sec. 1. JhuBei City,`
25			`// HsinChu County, Taiwan`
26			`// 302`
27			`//`
28			`// web: http://www.terasic.com/`
29			`// email: support@terasic.com`
30			`//`
31			`// --------------------------------------------------------------------`
32			`//`
33			`// Major Functions: DE0 VGA`
34			`//`
35			`// --------------------------------------------------------------------`
36			`//`
37			`// Revision History :`
38			`// --------------------------------------------------------------------`
39			`// Ver :\| Author :\| Mod. Date :\| Changes Made:`
40
41			`// --------------------------------------------------------------------`
42
43
44			`module DE0_VGA`
45			`(`
46			`//////////////////// Clock Input ////////////////////`
47			`CLOCK_50, // 50 MHz`
48			`CLOCK_50_2, // 50 MHz`
49			`//////////////////// Push Button ////////////////////`
50			`BUTTON, // Pushbutton[2:0]`
51			`//////////////////// DPDT Switch ////////////////////`
52			`SW, // Toggle Switch[9:0]`
53			`//////////////////// 7-SEG Dispaly ////////////////////`
54			`HEX0_D, // Seven Segment Digit 0`
55			`HEX0_DP, // Seven Segment Digit DP 0`
56			`HEX1_D, // Seven Segment Digit 1`
57			`HEX1_DP, // Seven Segment Digit DP 1`
58			`HEX2_D, // Seven Segment Digit 2`
59			`HEX2_DP, // Seven Segment Digit DP 2`
60			`HEX3_D, // Seven Segment Digit 3`
61			`HEX3_DP, // Seven Segment Digit DP 3`
62			`//////////////////////// LED ////////////////////////`
63			`LEDG, // LED Green[9:0]`
64			`//////////////////////// UART ////////////////////////`
65			`UART_TXD, // UART Transmitter`
66			`UART_RXD, // UART Receiver`
67			`UART_CTS, // UART Clear To Send`
68			`UART_RTS, // UART Request To Send`
69			`///////////////////// SDRAM Interface ////////////////`
70			`DRAM_DQ, // SDRAM Data bus 16 Bits`
71			`DRAM_ADDR, // SDRAM Address bus 13 Bits`
72			`DRAM_LDQM, // SDRAM Low-byte Data Mask`
73			`DRAM_UDQM, // SDRAM High-byte Data Mask`
74			`DRAM_WE_N, // SDRAM Write Enable`
75			`DRAM_CAS_N, // SDRAM Column Address Strobe`
76			`DRAM_RAS_N, // SDRAM Row Address Strobe`
77			`DRAM_CS_N, // SDRAM Chip Select`
78			`DRAM_BA_0, // SDRAM Bank Address 0`
79			`DRAM_BA_1, // SDRAM Bank Address 1`
80			`DRAM_CLK, // SDRAM Clock`
81			`DRAM_CKE, // SDRAM Clock Enable`
82			`//////////////////// Flash Interface ////////////////`
83			`FL_DQ, // FLASH Data bus 15 Bits`
84			`FL_DQ15_AM1, // FLASH Data bus Bit 15 or Address A-1`
85			`FL_ADDR, // FLASH Address bus 22 Bits`
86			`FL_WE_N, // FLASH Write Enable`
87			`FL_RST_N, // FLASH Reset`
88			`FL_OE_N, // FLASH Output Enable`
89			`FL_CE_N, // FLASH Chip Enable`
90			`FL_WP_N, // FLASH Hardware Write Protect`
91			`FL_BYTE_N, // FLASH Selects 8/16-bit mode`
92			`FL_RY, // FLASH Ready/Busy`
93			`//////////////////// LCD Module 16X2 ////////////////`
94			`LCD_BLON, // LCD Back Light ON/OFF`
95			`LCD_RW, // LCD Read/Write Select, 0 = Write, 1 = Read`
96			`LCD_EN, // LCD Enable`
97			`LCD_RS, // LCD Command/Data Select, 0 = Command, 1 = Data`
98			`LCD_DATA, // LCD Data bus 8 bits`
99			`//////////////////// SD_Card Interface ////////////////`
100			`SD_DAT0, // SD Card Data 0`
101			`SD_DAT3, // SD Card Data 3`
102			`SD_CMD, // SD Card Command Signal`
103			`SD_CLK, // SD Card Clock`
104			`SD_WP_N, // SD Card Write Protect`
105			`//////////////////// PS2 ////////////////////////////`
106			`PS2_KBDAT, // PS2 Keyboard Data`
107			`PS2_KBCLK, // PS2 Keyboard Clock`
108			`PS2_MSDAT, // PS2 Mouse Data`
109			`PS2_MSCLK, // PS2 Mouse Clock`
110			`//////////////////// VGA ////////////////////////////`
111			`VGA_HS, // VGA H_SYNC`
112			`VGA_VS, // VGA V_SYNC`
113			`VGA_R, // VGA Red[3:0]`
114			`VGA_G, // VGA Green[3:0]`
115			`VGA_B, // VGA Blue[3:0]`
116			`//////////////////// GPIO ////////////////////////////`
117			`GPIO0_CLKIN, // GPIO Connection 0 Clock In Bus`
118			`GPIO0_CLKOUT, // GPIO Connection 0 Clock Out Bus`
119			`GPIO0_D, // GPIO Connection 0 Data Bus`
120			`GPIO1_CLKIN, // GPIO Connection 1 Clock In Bus`
121			`GPIO1_CLKOUT, // GPIO Connection 1 Clock Out Bus`
122			`GPIO1_D // GPIO Connection 1 Data Bus`
123			`);`
124
125			`parameter R_SZ= 128;`
126
127
128			`//////////////////////// Clock Input ////////////////////////`
129			`input CLOCK_50; // 50 MHz`
130			`input CLOCK_50_2; // 50 MHz`
131			`//////////////////////// Push Button ////////////////////////`
132			`input [2:0] BUTTON; // Pushbutton[2:0]`
133			`//////////////////////// DPDT Switch ////////////////////////`
134			`input [9:0] SW; // Toggle Switch[9:0]`
135			`//////////////////////// 7-SEG Dispaly ////////////////////////`
136			`output [6:0] HEX0_D; // Seven Segment Digit 0`
137			`output HEX0_DP; // Seven Segment Digit DP 0`
138			`output [6:0] HEX1_D; // Seven Segment Digit 1`
139			`output HEX1_DP; // Seven Segment Digit DP 1`
140			`output [6:0] HEX2_D; // Seven Segment Digit 2`
141			`output HEX2_DP; // Seven Segment Digit DP 2`
142			`output [6:0] HEX3_D; // Seven Segment Digit 3`
143			`output HEX3_DP; // Seven Segment Digit DP 3`
144			`//////////////////////////// LED ////////////////////////////`
145			`output [9:0] LEDG; // LED Green[9:0]`
146			`//////////////////////////// UART ////////////////////////////`
147			`output UART_TXD; // UART Transmitter`
148			`input UART_RXD; // UART Receiver`
149			`output UART_CTS; // UART Clear To Send`
150			`input UART_RTS; // UART Request To Send`
151			`/////////////////////// SDRAM Interface ////////////////////////`
152			`inout [15:0] DRAM_DQ; // SDRAM Data bus 16 Bits`
153			`output [12:0] DRAM_ADDR; // SDRAM Address bus 13 Bits`
154			`output DRAM_LDQM; // SDRAM Low-byte Data Mask`
155			`output DRAM_UDQM; // SDRAM High-byte Data Mask`
156			`output DRAM_WE_N; // SDRAM Write Enable`
157			`output DRAM_CAS_N; // SDRAM Column Address Strobe`
158			`output DRAM_RAS_N; // SDRAM Row Address Strobe`
159			`output DRAM_CS_N; // SDRAM Chip Select`
160			`output DRAM_BA_0; // SDRAM Bank Address 0`
161			`output DRAM_BA_1; // SDRAM Bank Address 1`
162			`output DRAM_CLK; // SDRAM Clock`
163			`output DRAM_CKE; // SDRAM Clock Enable`
164			`//////////////////////// Flash Interface ////////////////////////`
165			`inout [14:0] FL_DQ; // FLASH Data bus 15 Bits`
166			`inout FL_DQ15_AM1; // FLASH Data bus Bit 15 or Address A-1`
167			`output [21:0] FL_ADDR; // FLASH Address bus 22 Bits`
168			`output FL_WE_N; // FLASH Write Enable`
169			`output FL_RST_N; // FLASH Reset`
170			`output FL_OE_N; // FLASH Output Enable`
171			`output FL_CE_N; // FLASH Chip Enable`
172			`output FL_WP_N; // FLASH Hardware Write Protect`
173			`output FL_BYTE_N; // FLASH Selects 8/16-bit mode`
174			`input FL_RY; // FLASH Ready/Busy`
175			`//////////////////// LCD Module 16X2 ////////////////////////////`
176			`inout [7:0] LCD_DATA; // LCD Data bus 8 bits`
177			`output LCD_BLON; // LCD Back Light ON/OFF`
178			`output LCD_RW; // LCD Read/Write Select, 0 = Write, 1 = Read`
179			`output LCD_EN; // LCD Enable`
180			`output LCD_RS; // LCD Command/Data Select, 0 = Command, 1 = Data`
181			`//////////////////// SD Card Interface ////////////////////////`
182			`inout SD_DAT0; // SD Card Data 0`
183			`inout SD_DAT3; // SD Card Data 3`
184			`inout SD_CMD; // SD Card Command Signal`
185			`output SD_CLK; // SD Card Clock`
186			`input SD_WP_N; // SD Card Write Protect`
187			`//////////////////////// PS2 ////////////////////////////////`
188			`inout PS2_KBDAT; // PS2 Keyboard Data`
189			`inout PS2_KBCLK; // PS2 Keyboard Clock`
190			`inout PS2_MSDAT; // PS2 Mouse Data`
191			`inout PS2_MSCLK; // PS2 Mouse Clock`
192			`//////////////////////// VGA ////////////////////////////`
193			`output VGA_HS; // VGA H_SYNC`
194			`output VGA_VS; // VGA V_SYNC`
195			`output [3:0] VGA_R; // VGA Red[3:0]`
196			`output [3:0] VGA_G; // VGA Green[3:0]`
197			`output [3:0] VGA_B; // VGA Blue[3:0]`
198			`//////////////////////// GPIO ////////////////////////////////`
199			`input [1:0] GPIO0_CLKIN; // GPIO Connection 0 Clock In Bus`
200			`output [1:0] GPIO0_CLKOUT; // GPIO Connection 0 Clock Out Bus`
201			`inout [31:0] GPIO0_D; // GPIO Connection 0 Data Bus`
202			`input [1:0] GPIO1_CLKIN; // GPIO Connection 1 Clock In Bus`
203			`output [1:0] GPIO1_CLKOUT; // GPIO Connection 1 Clock Out Bus`
204			`inout [31:0] GPIO1_D; // GPIO Connection 1 Data Bus`
205
206			`//=======================================================`
207			`// REG/WIRE declarations`
208			`//=======================================================`
209			`// All inout port turn to tri-state`
210			`assign DRAM_DQ = 16'hzzzz;`
211			`assign FL_DQ = 16'hzzzz;`
212			`assign LCD_DATA = 8'hzz;`
213			`assign SD_DAT0 = 1'hz;`
214			`assign SD_DAT3 = 1'hz;`
215			`assign SD_CMD = 1'hz;`
216			`assign PS2_KBDAT = 1'hz;`
217			`assign PS2_KBCLK = 1'hz;`
218			`assign PS2_MSDAT = 1'hz;`
219			`assign PS2_MSCLK = 1'hz;`
220			`assign GPIO0_D = 32'hzzzzzzzz;`
221			`assign GPIO1_D = 32'hzzzzzzzz;`
222
223			`//assign HEX0_D = 7'h7F;`
224			`assign HEX0_DP = ~seg_first;`
225			`//assign HEX1_D = 7'h7F;`
226			`assign HEX1_DP = ~seg_first;`
227			`//assign HEX2_D = 7'h7F;`
228			`assign HEX2_DP = ~seg_first;`
229			`//assign HEX3_D = 7'h7F;`
230			`assign HEX3_DP = ~seg_first;`
231
232			`assign LEDG = 10'h000;`
233			`//////////////////////// VGA ////////////////////////////`
234			`wire VGA_CTRL_CLK;`
235			`wire [11:0] mVGA_X;`
236			`wire [11:0] mVGA_Y;`
237			`wire [9:0] mVGA_R;`
238			`wire [9:0] mVGA_G;`
239			`wire [9:0] mVGA_B;`
240
241			`wire [9:0] sVGA_R;`
242			`wire [9:0] sVGA_G;`
243			`wire [9:0] sVGA_B;`
244			`assign VGA_R = sVGA_R[7:4];`
245			`assign VGA_G = sVGA_G[7:4];`
246			`assign VGA_B = sVGA_B[7:4];`
247
248			`//=======================================================`
249			`// Structural coding`
250			`//=======================================================`
251
252			`//////////////////////// VGA ////////////////////////////`
253
254
255			`VGA_CLK u1_1240x1024`
256			`( .inclk0(CLOCK_50),`
257			`.c0(VGA_CTRL_CLK)`
258			`);`
259			`defparam u1_1240x1024.PLL_MUL= 54;`
260			`defparam u1_1240x1024.PLL_DIV= 25;`
261
262
263			`VGA_Ctrl u2_1240x1024`
264			`( // Host Side`
265			`.oCurrent_X(mVGA_X),`
266			`.oCurrent_Y(mVGA_Y),`
267			`.iRed(mVGA_R),`
268			`.iGreen(mVGA_G),`
269			`.iBlue(mVGA_B),`
270			`// VGA Side`
271			`.oVGA_R(sVGA_R),`
272			`.oVGA_G(sVGA_G),`
273			`.oVGA_B(sVGA_B),`
274			`.oVGA_HS(VGA_HS),`
275			`.oVGA_VS(VGA_VS),`
276			`.oVGA_SYNC(),`
277			`.oVGA_BLANK(),`
278			`.oVGA_CLOCK(),`
279			`// Control Signal`
280			`.iCLK(VGA_CTRL_CLK),`
281			`.iRST_N(BUTTON[0]),`
282			`.les_btn(BUTTON[1])`
283			`);`
284			`defparam u2_1240x1024.H_FRONT = 48;`
285			`defparam u2_1240x1024.H_SYNC = 112;`
286			`defparam u2_1240x1024.H_BACK = 248;`
287			`defparam u2_1240x1024.H_ACT = 1280;`
288			`defparam u2_1240x1024.V_FRONT = 1;`
289			`defparam u2_1240x1024.V_SYNC = 3;`
290			`defparam u2_1240x1024.V_BACK = 38;`
291			`defparam u2_1240x1024.V_ACT = 1024;`
292
293			`wire [63:0] dbg_val;`
294
295			`VGA_Pattern #( R_SZ ) u3`
296			`( // Read Out Side`
297			`.oRed(mVGA_R),`
298			`.oGreen(mVGA_G),`
299			`.oBlue(mVGA_B),`
300			`.iVGA_X(mVGA_X),`
301			`.iVGA_Y(mVGA_Y),`
302			`.iVGA_CLK(VGA_CTRL_CLK),`
303			`// Control Signals`
304			`.iRST_n(BUTTON[0]),`
305			`.iColor_SW(SW),`
306			`.endFrame(VGA_VS),`
307			`.dbg_val(dbg_val)`
308			`);`
309
310			`wire [15:0] indicated_part;`
311			`wire seg_first;`
312
313			`dbg_7seg dbg_num`
314			`( .val( dbg_val ),`
315			`.show_next(BUTTON[1]),`
316			`.part( indicated_part ),`
317			`.is_first( seg_first ) );`
318
319			`SEG7_LUT_4 u0`
320			`( .oSEG0(HEX0_D),`
321			`.oSEG1(HEX1_D),`
322			`.oSEG2(HEX2_D),`
323			`.oSEG3(HEX3_D),`
324			`.iDIG( indicated_part )`
325			`);`
326
327
328			`endmodule`