OpenCores
URL https://opencores.org/ocsvn/numbert_sort_device/numbert_sort_device/trunk

Subversion Repositories numbert_sort_device

[/] [numbert_sort_device/] [trunk/] [boards/] [DE2-115/] [DE2_115_VGA.v] - Blame information for rev 2

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 leshabiruk
 
2
//=======================================================
3
//  This code is generated by Terasic System Builder
4
//=======================================================
5
 
6
module DE2_115_VGA(
7
 
8
        //////////// CLOCK //////////
9
        CLOCK_50,
10
        CLOCK2_50,
11
        CLOCK3_50,
12
 
13
        //////////// KEY //////////
14
        KEY,
15
 
16
        //////////// SW //////////
17
        SW,
18
 
19
        //////////// SEG7 //////////
20
        HEX0,
21
        HEX1,
22
        HEX2,
23
        HEX3,
24
        HEX4,
25
        HEX5,
26
        HEX6,
27
        HEX7,
28
 
29
        //////////// VGA //////////
30
        VGA_B,
31
        VGA_BLANK_N,
32
        VGA_CLK,
33
        VGA_G,
34
        VGA_HS,
35
        VGA_R,
36
        VGA_SYNC_N,
37
        VGA_VS
38
);
39
 
40
//=======================================================
41
//  PARAMETER declarations
42
//=======================================================
43
 
44
parameter R_SZ= 512;
45
 
46
 
47
//=======================================================
48
//  PORT declarations
49
//=======================================================
50
 
51
//////////// CLOCK //////////
52
input                                   CLOCK_50;
53
input                                   CLOCK2_50;
54
input                                   CLOCK3_50;
55
 
56
//////////// KEY //////////
57
input                [3:0]               KEY;
58
 
59
//////////// SW //////////
60
input               [17:0]               SW;
61
 
62
//////////// SEG7 //////////
63
output               [6:0]               HEX0;
64
output               [6:0]               HEX1;
65
output               [6:0]               HEX2;
66
output               [6:0]               HEX3;
67
output               [6:0]               HEX4;
68
output               [6:0]               HEX5;
69
output               [6:0]               HEX6;
70
output               [6:0]               HEX7;
71
 
72
//////////// VGA //////////
73
output               [7:0]               VGA_B;
74
output                                  VGA_BLANK_N;
75
output                                  VGA_CLK;
76
output               [7:0]               VGA_G;
77
output                                  VGA_HS;
78
output               [7:0]               VGA_R;
79
output                                  VGA_SYNC_N;
80
output                                  VGA_VS;
81
 
82
 
83
//=======================================================
84
//  REG/WIRE declarations
85
//=======================================================
86
 
87
wire                    VGA_CTRL_CLK_1240x1024;
88
wire                    VGA_CTRL_CLK= VGA_CTRL_CLK_1240x1024;
89
assign VGA_CLK= VGA_CTRL_CLK;
90
 
91
wire                    VGA_HS_1240x1024;
92
wire                    VGA_VS_1240x1024;
93
assign                  VGA_HS= VGA_HS_1240x1024;       //      VGA H_SYNC
94
assign                  VGA_VS= VGA_VS_1240x1024;       //      VGA V_SYNC
95
 
96
wire    [11:0]   mVGA_X;
97
wire    [11:0]   mVGA_Y;
98
 
99
wire    [9:0]    mVGA_R;
100
wire    [9:0]    mVGA_G;
101
wire    [9:0]    mVGA_B;
102
 
103
wire    [9:0]    sVGA_R_1240x1024;
104
wire    [9:0]    sVGA_G_1240x1024;
105
wire    [9:0]    sVGA_B_1240x1024;
106
wire    [9:0]    sVGA_R= sVGA_R_1240x1024;
107
wire    [9:0]    sVGA_G= sVGA_G_1240x1024;
108
wire    [9:0]    sVGA_B= sVGA_B_1240x1024;
109
 
110
 
111
assign  VGA_R   =       sVGA_R[7:0];
112
assign  VGA_G   =       sVGA_G[7:0];
113
assign  VGA_B   =       sVGA_B[7:0];
114
 
115
//=======================================================
116
//  Structural coding
117
//=======================================================
118
 
119
VGA_CLK         u1_1240x1024
120
                (       .inclk0(CLOCK_50),
121
                        .c0( VGA_CTRL_CLK_1240x1024 )
122
                );
123
                defparam u1_1240x1024.PLL_MUL= 54;
124
                defparam u1_1240x1024.PLL_DIV= 25;
125
 
126
 
127
VGA_Ctrl        u2_1240x1024
128
                (       //      Host Side
129
                        .oCurrent_X( mVGA_X),
130
                        .oCurrent_Y( mVGA_Y),
131
                        .iRed( mVGA_R),
132
                        .iGreen( mVGA_G),
133
                        .iBlue( mVGA_B),
134
                        //      VGA Side
135
                        .oVGA_R( sVGA_R_1240x1024 ),
136
                        .oVGA_G( sVGA_G_1240x1024 ),
137
                        .oVGA_B( sVGA_B_1240x1024 ),
138
                        .oVGA_HS( VGA_HS_1240x1024 ),
139
                        .oVGA_VS( VGA_VS_1240x1024 ),
140
                        .oVGA_SYNC( VGA_SYNC_N ),
141
                        .oVGA_BLANK( VGA_BLANK_N ),
142
                        .oVGA_CLOCK(),
143
                        //      Control Signal
144
                        .iCLK( VGA_CTRL_CLK),
145
                        .iRST_N( KEY[0]),
146
                        .les_btn( KEY[2])
147
                );
148
                defparam        u2_1240x1024.H_FRONT    =       48;
149
                defparam        u2_1240x1024.H_SYNC     =       112;
150
                defparam        u2_1240x1024.H_BACK     =       248;
151
                defparam        u2_1240x1024.H_ACT      =       1280;
152
                defparam        u2_1240x1024.V_FRONT    =       1;
153
                defparam        u2_1240x1024.V_SYNC     =       3;
154
                defparam        u2_1240x1024.V_BACK     =       38;
155
                defparam        u2_1240x1024.V_ACT      =       1024;
156
 
157
wire [31:0]VGenOut;
158
parameter RES_X_H= 1240;
159
parameter RES_Y_H= 1024;
160
parameter XY_STEP_H= 7;
161
wire signed [11:0] x;
162
wire signed [11:0] y;
163
assign x= (mVGA_X- RES_X_H/2);
164
assign y= (mVGA_Y- RES_Y_H/2);
165
wire [31:0] X_in= x<<<XY_STEP_H;
166
wire [31:0] Y_in= y<<<XY_STEP_H;
167
 
168
VGA_Pattern #( R_SZ )   u3
169
                (       //      Read Out Side
170
                        .oRed(mVGA_R),
171
                        .oGreen(mVGA_G),
172
                        .oBlue(mVGA_B),
173
                        .iVGA_X(mVGA_X),
174
                        .iVGA_Y(mVGA_Y),
175
                        .iVGA_CLK(VGA_CTRL_CLK),
176
                        //      Control Signals
177
                        .iRST_n(KEY[0]),
178
                        .iColor_SW(SW),
179
                        .endFrame(VGA_VS),
180
                        .dbg_val(dbg_val)
181
                );
182
 
183
wire [63:0] dbg_val;
184
wire [15:0] indicated_part;
185
wire seg_first;
186
 
187
dbg_7seg dbg_num
188
                (  .val( dbg_val ),
189
                        .show_next(KEY[2]),
190
                        .part( indicated_part ),
191
                        .is_first( seg_first ) );
192
 
193
SEG7_LUT_4      u0
194
                (       .oSEG0(HEX0),
195
                        .oSEG1(HEX1),
196
                        .oSEG2(HEX2),
197
                        .oSEG3(HEX3),
198
                        .iDIG( indicated_part )
199
                );
200
 
201
 
202
endmodule

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.