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[/] [numbert_sort_device/] [trunk/] [utility/] [VGA_Ctrl.v] - Blame information for rev 2

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1 2 leshabiruk 
module  VGA_Ctrl        (       //      Host Side
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                                                iRed,
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                                                iGreen,
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                                                iBlue,
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                                                oCurrent_X,
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                                                oCurrent_Y,
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                                                //      VGA Side
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                                                oVGA_R,
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                                                oVGA_G,
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                                                oVGA_B,
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                                                oVGA_HS,
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                                                oVGA_VS,
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                                                oVGA_SYNC,
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                                                oVGA_BLANK,
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                                                oVGA_CLOCK,
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                                                //      Control Signal
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                                                iCLK,
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                                                iRST_N,
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                                                les_btn );
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input wire les_btn;
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//      Host Side
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input           [9:0]    iRed;
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input           [9:0]    iGreen;
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input           [9:0]    iBlue;
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output          [10:0]   oCurrent_X;
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output          [10:0]   oCurrent_Y;
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//      VGA Side
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output          [9:0]    oVGA_R;
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output          [9:0]    oVGA_G;
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output          [9:0]    oVGA_B;
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output  reg                     oVGA_HS;
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output  reg                     oVGA_VS;
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output                          oVGA_SYNC;
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output                          oVGA_BLANK;
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output                          oVGA_CLOCK;
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//      Control Signal
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input                           iCLK;
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input                           iRST_N;
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//      Internal Registers
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reg                     [10:0]   H_Cont;
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reg                     [10:0]   V_Cont;
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////////////////////////////////////////////////////////////
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//      Horizontal      Parameter
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parameter       H_FRONT =       16;
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parameter       H_SYNC  =       96;
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parameter       H_BACK  =       48;
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parameter       H_ACT   =       640;
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//      Vertical Parameter
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parameter       V_FRONT =       10;
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parameter       V_SYNC  =       2;
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parameter       V_BACK  =       33;
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parameter       V_ACT   =       480;
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////////////////////////////////////////////////////////////
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parameter       H_BLANK =       H_FRONT+H_SYNC+H_BACK;
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parameter       H_TOTAL =       H_FRONT+H_SYNC+H_BACK+H_ACT;
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parameter       V_BLANK =       V_FRONT+V_SYNC+V_BACK;
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parameter       V_TOTAL =       V_FRONT+V_SYNC+V_BACK+V_ACT;
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////////////////////////////////////////////////////////////
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assign  oVGA_SYNC       =       1'b1;                   //      This pin is unused.
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assign  oVGA_BLANK      =       ~((H_Cont<H_BLANK)||(V_Cont<V_BLANK));
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assign  oVGA_CLOCK      =       ~iCLK;
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assign  oVGA_R          =       (oCurrent_X > 0) ?       iRed : 0 ;
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assign  oVGA_G          =       (oCurrent_X > 0) ?       iGreen : 0 ;
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assign  oVGA_B          =       (oCurrent_X > 0) ?       iBlue : 0 ;
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assign  oCurrent_X      =       (H_Cont>=H_BLANK)       ?       H_Cont-H_BLANK  :       11'h0   ;
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assign  oCurrent_Y      =       (V_Cont>=V_BLANK)       ?       V_Cont-V_BLANK  :       11'h0   ;
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//reg [9:0] V_ACT;
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//reg [9:0] V_TOTAL;
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reg [7:0] btn_cnt;
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always@(posedge les_btn)
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begin
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        btn_cnt= btn_cnt +8'h1;
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end
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//      Horizontal Generator: Refer to the pixel clock
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always@(posedge iCLK or negedge iRST_N)
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begin
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        if(!iRST_N)
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        begin
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                H_Cont          <=      0;
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                oVGA_HS         <=      1;
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//              V_ACT   <=      480 +btn_cnt;
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        //      V_TOTAL =       V_FRONT+V_SYNC+V_BACK+V_ACT;
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        end
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        else
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        begin
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//              if(H_Cont<H_TOTAL)
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                if(H_Cont<H_TOTAL-1)
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                H_Cont  <=      H_Cont+1'b1;
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                else
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                H_Cont  <=      0;
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                //      Horizontal Sync
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                if(H_Cont==H_FRONT-1)                   //      Front porch end
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                oVGA_HS <=      1'b0;
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                else if(H_Cont==H_FRONT+H_SYNC-1)       //      Sync pulse end
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                oVGA_HS <=      1'b1;
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        end
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end
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//      Vertical Generator: Refer to the horizontal sync
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always@(posedge oVGA_HS or negedge iRST_N)
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begin
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        if(!iRST_N)
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        begin
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                V_Cont          <=      0;
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                oVGA_VS         <=      1;
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        end
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        else
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        begin
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//              if(V_Cont<V_TOTAL)
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                if(V_Cont<V_TOTAL-1)
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                        V_Cont  <=      V_Cont+1'b1;
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                else
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                        V_Cont  <=      0;
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                //      Vertical Sync
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                if(V_Cont==V_FRONT-1)                   //      Front porch end
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                        oVGA_VS <=      1'b0;
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                if(V_Cont==V_FRONT+V_SYNC-1)    //      Sync pulse end
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                        oVGA_VS <=      1'b1;
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        end
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end
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endmodule

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