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//cont_controller.v
/*
Distributed under the MIT license.
Copyright (c) 2011 Dave McCoy (dave.mccoy@cospandesign.com)
 
Permission is hereby granted, free of charge, to any person obtaining a copy of
this software and associated documentation files (the "Software"), to deal in
the Software without restriction, including without limitation the rights to
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
of the Software, and to permit persons to whom the Software is furnished to do
so, subject to the following conditions:
 
The above copyright notice and this permission notice shall be included in all
copies or substantial portions of the Software.
 
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
SOFTWARE.
*/
 
`include "sata_defines.v"
 
module cont_controller (
 
 
input               rst,            //reset
input               clk,
input               phy_ready,
input               xmit_cont_en,   //enable the transmit cont primative (slows simulations WAY!!! down)
 
input               last_prim,
 
 
input       [31:0]  ll_tx_din,
input               ll_tx_isk,
 
output      [31:0]  cont_tx_dout,
output              cont_tx_isk,
 
input       [31:0]  rx_din,
input       [3:0]   rx_isk,
 
output              detect_sync,
output              detect_r_rdy,
output              detect_r_ip,
output              detect_r_err,
output              detect_r_ok,
output              detect_x_rdy,
output              detect_sof,
output              detect_eof,
output              detect_wtrm,
output              detect_cont,
output              detect_hold,
output              detect_holda,
output              detect_preq_s,
output              detect_preq_p,
output              detect_align,
 
output              detect_xrdy_xrdy
);
 
//Parameters
//Registers/Wires
 
//CONT detect State Machine
wire                hold_cont;
wire                holda_cont;
wire                pmreq_p_cont;
wire                pmreq_s_cont;
wire                r_err_cont;
wire                r_ip_cont;
wire                r_ok_cont;
wire                r_rdy_cont;
wire                sync_cont;
wire                wtrm_cont;
wire                x_rdy_cont;
 
reg                 cont_detect;
 
reg         [31:0]  prev_prim;
 
reg                 hold_cont_ready;
reg                 holda_cont_ready;
reg                 pmreq_p_cont_ready;
reg                 pmreq_s_cont_ready;
reg                 r_err_cont_ready;
reg                 r_ip_cont_ready;
reg                 r_ok_cont_ready;
reg                 r_rdy_cont_ready;
reg                 sync_cont_ready;
reg                 wtrm_cont_ready;
reg                 x_rdy_cont_ready;
 
 
//CONT generate state machine
reg       [31:0]    tx_prev_prim;
reg                 tx_cont_enable;
reg                 tx_cont_sent;
reg                 send_cont;
 
//Scrambler control
wire                scram_en;
wire      [31:0]    scram_dout;
 
 
//Submodules
scrambler scram (
  .rst            (rst              ),
  .clk            (clk              ),
  .prim_scrambler (1'b1             ),
  .en             (scram_en         ),
  .din            (ll_tx_din        ),
  .dout           (scram_dout       )
);
 
//Asynchronous Logic
assign  detect_sync   = ((rx_isk[0])     && (rx_din == `PRIM_SYNC    )) ||  sync_cont;   //sync (normal) == sync(cont)
assign  detect_r_rdy  = ((rx_isk[0])     && (rx_din == `PRIM_R_RDY   )) ||  r_rdy_cont;
assign  detect_r_ip   = ((rx_isk[0])     && (rx_din == `PRIM_R_IP    )) ||  r_ip_cont;
assign  detect_r_err  = ((rx_isk[0])     && (rx_din == `PRIM_R_ERR   )) ||  r_err_cont;
assign  detect_r_ok   = ((rx_isk[0])     && (rx_din == `PRIM_R_OK    )) ||  r_ok_cont;
assign  detect_x_rdy  = ((rx_isk[0])     && (rx_din == `PRIM_X_RDY   )) ||  x_rdy_cont;
assign  detect_sof    = (rx_isk[0])      && (rx_din == `PRIM_SOF     );
assign  detect_eof    = (rx_isk[0])      && (rx_din == `PRIM_EOF     );
assign  detect_wtrm   = ((rx_isk[0])     && (rx_din == `PRIM_WTRM    )) ||  wtrm_cont;
assign  detect_cont   = (rx_isk[0])      && (rx_din == `PRIM_CONT    );
assign  detect_hold   = ((rx_isk[0])     && (rx_din == `PRIM_HOLD    )) ||  hold_cont;  //hold  (normal) == hold  (cont)
assign  detect_holda  = ((rx_isk[0])     && (rx_din == `PRIM_HOLDA   )) ||  holda_cont; //holda (normal) == holda (cont)
assign  detect_preq_s = ((rx_isk[0])     && (rx_din == `PRIM_PREQ_S  )) ||  pmreq_s_cont;
assign  detect_preq_p = ((rx_isk[0])     && (rx_din == `PRIM_PREQ_P  )) ||  pmreq_p_cont;
assign  detect_align  = (rx_isk[0])      && (rx_din == `PRIM_ALIGN   );
 
assign  detect_xrdy_xrdy  = ((((rx_isk[0])&& (rx_din == `PRIM_X_RDY   )) ||  x_rdy_cont) && ll_tx_isk && (ll_tx_din == `PRIM_X_RDY));
 
assign  sync_cont     =   sync_cont_ready    && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
assign  hold_cont     =   hold_cont_ready    && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
assign  holda_cont    =   holda_cont_ready   && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
assign  pmreq_p_cont  =   pmreq_p_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
assign  pmreq_s_cont  =   pmreq_s_cont_ready && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
assign  r_err_cont    =   r_err_cont_ready   && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
assign  r_ip_cont     =   r_ip_cont_ready    && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
assign  r_ok_cont     =   r_ok_cont_ready    && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
assign  r_rdy_cont    =   r_rdy_cont_ready   && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
assign  wtrm_cont     =   wtrm_cont_ready    && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
assign  x_rdy_cont    =   x_rdy_cont_ready   && ((rx_din == `PRIM_CONT) || (!rx_isk[0] || detect_align));
 
 
assign  cont_tx_dout  = (!xmit_cont_en) ? ll_tx_din :                           //when transmit cont gen is disable
                      ((tx_prev_prim != ll_tx_din) && ll_tx_isk) ? ll_tx_din :  //if the prev != curr (exit)
                        (last_prim)      ? ll_tx_din:
                        (tx_cont_enable) ?                                      //if the cont is enabled
                          send_cont ?   `PRIM_CONT  :                           //need to first send the cont
                                        scram_dout  :                           //send the junk
                                          ll_tx_din;                            //tx cont is not enabled
 
assign  cont_tx_isk   = (!xmit_cont_en) ? ll_tx_isk :
                        ((tx_prev_prim != ll_tx_din) && ll_tx_isk) ? ll_tx_isk ://if the prev != curr (exit)
                        (last_prim)      ?ll_tx_isk:
                        (tx_cont_enable) ?                                      //if the cont is enabled
                          send_cont ?   1 :                                     //need to first send the cont
 
                                          ll_tx_isk;                            //tx cont is not enabled
assign  scram_en      = tx_cont_enable;
 
//Synchronous logic
 
//Cont detect
always @ (posedge clk) begin
  if (rst) begin
    cont_detect             <=  0;
 
    hold_cont_ready         <=  0;
    holda_cont_ready        <=  0;
    pmreq_p_cont_ready      <=  0;
    pmreq_s_cont_ready      <=  0;
    r_err_cont_ready        <=  0;
    r_ip_cont_ready         <=  0;
    r_ok_cont_ready         <=  0;
    r_rdy_cont_ready        <=  0;
    sync_cont_ready         <=  0;
    wtrm_cont_ready         <=  0;
    x_rdy_cont_ready        <=  0;
 
  end
  else begin
    if (!detect_align) begin
      if (rx_isk) begin
        if (rx_din == `PRIM_CONT) begin
          cont_detect                 <=  1;
        end
        else if (prev_prim == rx_din) begin
          case (prev_prim)
            `PRIM_SYNC   : begin
              sync_cont_ready         <=  1;
            end
            `PRIM_R_RDY  : begin
              r_rdy_cont_ready        <=  1;
            end
            `PRIM_R_IP   : begin
              r_ip_cont_ready         <=  1;
            end
            `PRIM_R_ERR  : begin
              r_err_cont_ready        <=  1;
            end
            `PRIM_R_OK   : begin
              r_ok_cont_ready         <=  1;
            end
            `PRIM_X_RDY  : begin
              x_rdy_cont_ready        <=  1;
            end
            `PRIM_WTRM   : begin
              wtrm_cont_ready         <=  1;
            end
            `PRIM_HOLD   : begin
              if (cont_detect) begin
                hold_cont_ready       <=  0;
                cont_detect           <=  0;
              end
              else begin
                hold_cont_ready       <=  1;
              end
            end
            `PRIM_HOLDA  : begin
              if (cont_detect) begin
                holda_cont_ready      <=  0;
                cont_detect           <=  0;
              end
              else begin
                holda_cont_ready      <=  1;
              end
            end
            `PRIM_PREQ_S : begin
              pmreq_s_cont_ready      <=  1;
            end
            `PRIM_PREQ_P : begin
              pmreq_p_cont_ready      <=  1;
            end
            `PRIM_ALIGN  : begin
            end
            default: begin
              hold_cont_ready         <=  0;
              holda_cont_ready        <=  0;
              pmreq_p_cont_ready      <=  0;
              pmreq_s_cont_ready      <=  0;
              r_err_cont_ready        <=  0;
              r_ip_cont_ready         <=  0;
              r_ok_cont_ready         <=  0;
              r_rdy_cont_ready        <=  0;
              sync_cont_ready         <=  0;
              wtrm_cont_ready         <=  0;
              x_rdy_cont_ready        <=  0;
            end
          endcase
        end
        //save the previous primative
        else begin
          prev_prim               <=  rx_din;
          //previous primative doesn't equal current primitive
          cont_detect             <=  0;
          hold_cont_ready         <=  0;
          holda_cont_ready        <=  0;
          pmreq_p_cont_ready      <=  0;
          pmreq_s_cont_ready      <=  0;
          r_err_cont_ready        <=  0;
          r_ip_cont_ready         <=  0;
          r_ok_cont_ready         <=  0;
          r_rdy_cont_ready        <=  0;
          sync_cont_ready         <=  0;
          wtrm_cont_ready         <=  0;
          x_rdy_cont_ready        <=  0;
 
        end
      end
      if (!rx_isk[0] && !cont_detect) begin
        cont_detect             <=  0;
        hold_cont_ready         <=  0;
        holda_cont_ready        <=  0;
        pmreq_p_cont_ready      <=  0;
        pmreq_s_cont_ready      <=  0;
        r_err_cont_ready        <=  0;
        r_ip_cont_ready         <=  0;
        r_ok_cont_ready         <=  0;
        r_rdy_cont_ready        <=  0;
        sync_cont_ready         <=  0;
        wtrm_cont_ready         <=  0;
        x_rdy_cont_ready        <=  0;
      end
    end
  end
end
 
 
//Cont Generator
always @ (posedge clk) begin
  if (rst || !xmit_cont_en) begin
    tx_prev_prim              <=  0;
    tx_cont_enable            <=  0;
    tx_cont_sent              <=  0;
    send_cont                 <=  0;
  end
  else begin
    if (phy_ready) begin
 
      send_cont               <=  0;
 
      if (ll_tx_isk) begin
 
        //reset everything because the previous primative is not equal to the current one
        if (tx_prev_prim != ll_tx_din) begin
          send_cont           <=  0;
          tx_cont_sent        <=  0;
          tx_cont_enable      <=  0;
        end
        else begin
 
          //see if we need to send the cont primative
          if (tx_cont_enable && send_cont) begin
            tx_cont_sent          <=  1;
          end
 
          //previous primative == current primative
          case (tx_prev_prim)
            `PRIM_SYNC   : begin
              tx_cont_enable     <=  1;
              if (!tx_cont_sent && !send_cont) begin
                send_cont          <=  1;
              end
            end
            `PRIM_R_RDY  : begin
              tx_cont_enable     <=  1;
              if (!tx_cont_sent && !send_cont) begin
                send_cont          <=  1;
              end
            end
            `PRIM_R_IP   : begin
              tx_cont_enable     <=  1;
              if (!tx_cont_sent && !send_cont) begin
                send_cont          <=  1;
              end
            end
            `PRIM_R_ERR  : begin
              tx_cont_enable     <=  1;
              if (!tx_cont_sent && !send_cont) begin
                send_cont          <=  1;
              end
            end
            `PRIM_R_OK   : begin
              tx_cont_enable     <=  1;
              if (!tx_cont_sent && !send_cont) begin
                send_cont          <=  1;
              end
            end
            `PRIM_X_RDY  : begin
              tx_cont_enable     <=  1;
              if (!tx_cont_sent && !send_cont) begin
                send_cont          <=  1;
              end
            end
            `PRIM_WTRM   : begin
              tx_cont_enable     <=  1;
              if (!tx_cont_sent && !send_cont) begin
                send_cont          <=  1;
              end
            end
            `PRIM_HOLD   : begin
              tx_cont_enable     <=  1;
              if (!tx_cont_sent && !send_cont) begin
                send_cont          <=  1;
              end
            end
            `PRIM_HOLDA  : begin
              tx_cont_enable     <=  1;
              if (!tx_cont_sent && !send_cont) begin
                send_cont          <=  1;
              end
            end
            `PRIM_PREQ_S : begin
              tx_cont_enable     <=  1;
              if (!tx_cont_sent && !send_cont) begin
                send_cont          <=  1;
              end
            end
            `PRIM_PREQ_P : begin
              tx_cont_enable     <=  1;
              if (!tx_cont_sent && !send_cont) begin
                send_cont          <=  1;
              end
            end
            default: begin
              send_cont         <=  0;
              tx_cont_enable    <=  0;
              tx_cont_sent      <=  0;
            end
          endcase
        end
      end
      else begin
        //it is not a k value so don't read it
        tx_prev_prim          <=  0;
      end
      //k value record the PRIM
      tx_prev_prim          <=  ll_tx_din;
 
      if (last_prim) begin
        tx_cont_enable      <=  0;
      end
    end
  end
end
 
 
 
endmodule
 

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[/] [nysa_sata/] [trunk/] [rtl/] [link/] [cont_controller.v] - Blame information for rev 2

Line No.	Rev	Author	Line
1	2	cospan	`//cont_controller.v`
2			`/*`
3			`Distributed under the MIT license.`
4			`Copyright (c) 2011 Dave McCoy (dave.mccoy@cospandesign.com)`
5
6			`Permission is hereby granted, free of charge, to any person obtaining a copy of`
7			`this software and associated documentation files (the "Software"), to deal in`
8			`the Software without restriction, including without limitation the rights to`
9			`use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies`
10			`of the Software, and to permit persons to whom the Software is furnished to do`
11			`so, subject to the following conditions:`
12
13			`The above copyright notice and this permission notice shall be included in all`
14			`copies or substantial portions of the Software.`
15
16			`THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR`
17			`IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,`
18			`FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE`
19			`AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER`
20			`LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,`
21			`OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE`
22			`SOFTWARE.`
23			`*/`
24
25			`include "sata_defines.v"
26
27			`module cont_controller (`
28
29
30			`input rst, //reset`
31			`input clk,`
32			`input phy_ready,`
33			`input xmit_cont_en, //enable the transmit cont primative (slows simulations WAY!!! down)`
34
35			`input last_prim,`
36
37
38			`input [31:0] ll_tx_din,`
39			`input ll_tx_isk,`
40
41			`output [31:0] cont_tx_dout,`
42			`output cont_tx_isk,`
43
44			`input [31:0] rx_din,`
45			`input [3:0] rx_isk,`
46
47			`output detect_sync,`
48			`output detect_r_rdy,`
49			`output detect_r_ip,`
50			`output detect_r_err,`
51			`output detect_r_ok,`
52			`output detect_x_rdy,`
53			`output detect_sof,`
54			`output detect_eof,`
55			`output detect_wtrm,`
56			`output detect_cont,`
57			`output detect_hold,`
58			`output detect_holda,`
59			`output detect_preq_s,`
60			`output detect_preq_p,`
61			`output detect_align,`
62
63			`output detect_xrdy_xrdy`
64			`);`
65
66			`//Parameters`
67			`//Registers/Wires`
68
69			`//CONT detect State Machine`
70			`wire hold_cont;`
71			`wire holda_cont;`
72			`wire pmreq_p_cont;`
73			`wire pmreq_s_cont;`
74			`wire r_err_cont;`
75			`wire r_ip_cont;`
76			`wire r_ok_cont;`
77			`wire r_rdy_cont;`
78			`wire sync_cont;`
79			`wire wtrm_cont;`
80			`wire x_rdy_cont;`
81
82			`reg cont_detect;`
83
84			`reg [31:0] prev_prim;`
85
86			`reg hold_cont_ready;`
87			`reg holda_cont_ready;`
88			`reg pmreq_p_cont_ready;`
89			`reg pmreq_s_cont_ready;`
90			`reg r_err_cont_ready;`
91			`reg r_ip_cont_ready;`
92			`reg r_ok_cont_ready;`
93			`reg r_rdy_cont_ready;`
94			`reg sync_cont_ready;`
95			`reg wtrm_cont_ready;`
96			`reg x_rdy_cont_ready;`
97
98
99			`//CONT generate state machine`
100			`reg [31:0] tx_prev_prim;`
101			`reg tx_cont_enable;`
102			`reg tx_cont_sent;`
103			`reg send_cont;`
104
105			`//Scrambler control`
106			`wire scram_en;`
107			`wire [31:0] scram_dout;`
108
109
110			`//Submodules`
111			`scrambler scram (`
112			`.rst (rst ),`
113			`.clk (clk ),`
114			`.prim_scrambler (1'b1 ),`
115			`.en (scram_en ),`
116			`.din (ll_tx_din ),`
117			`.dout (scram_dout )`
118			`);`
119
120			`//Asynchronous Logic`
121			assign detect_sync = ((rx_isk[0]) && (rx_din == `PRIM_SYNC )) \|\| sync_cont; //sync (normal) == sync(cont)
122			assign detect_r_rdy = ((rx_isk[0]) && (rx_din == `PRIM_R_RDY )) \|\| r_rdy_cont;
123			assign detect_r_ip = ((rx_isk[0]) && (rx_din == `PRIM_R_IP )) \|\| r_ip_cont;
124			assign detect_r_err = ((rx_isk[0]) && (rx_din == `PRIM_R_ERR )) \|\| r_err_cont;
125			assign detect_r_ok = ((rx_isk[0]) && (rx_din == `PRIM_R_OK )) \|\| r_ok_cont;
126			assign detect_x_rdy = ((rx_isk[0]) && (rx_din == `PRIM_X_RDY )) \|\| x_rdy_cont;
127			assign detect_sof = (rx_isk[0]) && (rx_din == `PRIM_SOF );
128			assign detect_eof = (rx_isk[0]) && (rx_din == `PRIM_EOF );
129			assign detect_wtrm = ((rx_isk[0]) && (rx_din == `PRIM_WTRM )) \|\| wtrm_cont;
130			assign detect_cont = (rx_isk[0]) && (rx_din == `PRIM_CONT );
131			assign detect_hold = ((rx_isk[0]) && (rx_din == `PRIM_HOLD )) \|\| hold_cont; //hold (normal) == hold (cont)
132			assign detect_holda = ((rx_isk[0]) && (rx_din == `PRIM_HOLDA )) \|\| holda_cont; //holda (normal) == holda (cont)
133			assign detect_preq_s = ((rx_isk[0]) && (rx_din == `PRIM_PREQ_S )) \|\| pmreq_s_cont;
134			assign detect_preq_p = ((rx_isk[0]) && (rx_din == `PRIM_PREQ_P )) \|\| pmreq_p_cont;
135			assign detect_align = (rx_isk[0]) && (rx_din == `PRIM_ALIGN );
136
137			assign detect_xrdy_xrdy = ((((rx_isk[0])&& (rx_din == `PRIM_X_RDY )) \|\| x_rdy_cont) && ll_tx_isk && (ll_tx_din == `PRIM_X_RDY));
138
139			assign sync_cont = sync_cont_ready && ((rx_din == `PRIM_CONT) \|\| (!rx_isk[0] \|\| detect_align));
140			assign hold_cont = hold_cont_ready && ((rx_din == `PRIM_CONT) \|\| (!rx_isk[0] \|\| detect_align));
141			assign holda_cont = holda_cont_ready && ((rx_din == `PRIM_CONT) \|\| (!rx_isk[0] \|\| detect_align));
142			assign pmreq_p_cont = pmreq_p_cont_ready && ((rx_din == `PRIM_CONT) \|\| (!rx_isk[0] \|\| detect_align));
143			assign pmreq_s_cont = pmreq_s_cont_ready && ((rx_din == `PRIM_CONT) \|\| (!rx_isk[0] \|\| detect_align));
144			assign r_err_cont = r_err_cont_ready && ((rx_din == `PRIM_CONT) \|\| (!rx_isk[0] \|\| detect_align));
145			assign r_ip_cont = r_ip_cont_ready && ((rx_din == `PRIM_CONT) \|\| (!rx_isk[0] \|\| detect_align));
146			assign r_ok_cont = r_ok_cont_ready && ((rx_din == `PRIM_CONT) \|\| (!rx_isk[0] \|\| detect_align));
147			assign r_rdy_cont = r_rdy_cont_ready && ((rx_din == `PRIM_CONT) \|\| (!rx_isk[0] \|\| detect_align));
148			assign wtrm_cont = wtrm_cont_ready && ((rx_din == `PRIM_CONT) \|\| (!rx_isk[0] \|\| detect_align));
149			assign x_rdy_cont = x_rdy_cont_ready && ((rx_din == `PRIM_CONT) \|\| (!rx_isk[0] \|\| detect_align));
150
151
152			`assign cont_tx_dout = (!xmit_cont_en) ? ll_tx_din : //when transmit cont gen is disable`
153			`((tx_prev_prim != ll_tx_din) && ll_tx_isk) ? ll_tx_din : //if the prev != curr (exit)`
154			`(last_prim) ? ll_tx_din:`
155			`(tx_cont_enable) ? //if the cont is enabled`
156			send_cont ? `PRIM_CONT : //need to first send the cont
157			`scram_dout : //send the junk`
158			`ll_tx_din; //tx cont is not enabled`
159
160			`assign cont_tx_isk = (!xmit_cont_en) ? ll_tx_isk :`
161			`((tx_prev_prim != ll_tx_din) && ll_tx_isk) ? ll_tx_isk ://if the prev != curr (exit)`
162			`(last_prim) ?ll_tx_isk:`
163			`(tx_cont_enable) ? //if the cont is enabled`
164			`send_cont ? 1 : //need to first send the cont`
165
166			`ll_tx_isk; //tx cont is not enabled`
167			`assign scram_en = tx_cont_enable;`
168
169			`//Synchronous logic`
170
171			`//Cont detect`
172			`always @ (posedge clk) begin`
173			`if (rst) begin`
174			`cont_detect <= 0;`
175
176			`hold_cont_ready <= 0;`
177			`holda_cont_ready <= 0;`
178			`pmreq_p_cont_ready <= 0;`
179			`pmreq_s_cont_ready <= 0;`
180			`r_err_cont_ready <= 0;`
181			`r_ip_cont_ready <= 0;`
182			`r_ok_cont_ready <= 0;`
183			`r_rdy_cont_ready <= 0;`
184			`sync_cont_ready <= 0;`
185			`wtrm_cont_ready <= 0;`
186			`x_rdy_cont_ready <= 0;`
187
188			`end`
189			`else begin`
190			`if (!detect_align) begin`
191			`if (rx_isk) begin`
192			if (rx_din == `PRIM_CONT) begin
193			`cont_detect <= 1;`
194			`end`
195			`else if (prev_prim == rx_din) begin`
196			`case (prev_prim)`
197			`PRIM_SYNC : begin
198			`sync_cont_ready <= 1;`
199			`end`
200			`PRIM_R_RDY : begin
201			`r_rdy_cont_ready <= 1;`
202			`end`
203			`PRIM_R_IP : begin
204			`r_ip_cont_ready <= 1;`
205			`end`
206			`PRIM_R_ERR : begin
207			`r_err_cont_ready <= 1;`
208			`end`
209			`PRIM_R_OK : begin
210			`r_ok_cont_ready <= 1;`
211			`end`
212			`PRIM_X_RDY : begin
213			`x_rdy_cont_ready <= 1;`
214			`end`
215			`PRIM_WTRM : begin
216			`wtrm_cont_ready <= 1;`
217			`end`
218			`PRIM_HOLD : begin
219			`if (cont_detect) begin`
220			`hold_cont_ready <= 0;`
221			`cont_detect <= 0;`
222			`end`
223			`else begin`
224			`hold_cont_ready <= 1;`
225			`end`
226			`end`
227			`PRIM_HOLDA : begin
228			`if (cont_detect) begin`
229			`holda_cont_ready <= 0;`
230			`cont_detect <= 0;`
231			`end`
232			`else begin`
233			`holda_cont_ready <= 1;`
234			`end`
235			`end`
236			`PRIM_PREQ_S : begin
237			`pmreq_s_cont_ready <= 1;`
238			`end`
239			`PRIM_PREQ_P : begin
240			`pmreq_p_cont_ready <= 1;`
241			`end`
242			`PRIM_ALIGN : begin
243			`end`
244			`default: begin`
245			`hold_cont_ready <= 0;`
246			`holda_cont_ready <= 0;`
247			`pmreq_p_cont_ready <= 0;`
248			`pmreq_s_cont_ready <= 0;`
249			`r_err_cont_ready <= 0;`
250			`r_ip_cont_ready <= 0;`
251			`r_ok_cont_ready <= 0;`
252			`r_rdy_cont_ready <= 0;`
253			`sync_cont_ready <= 0;`
254			`wtrm_cont_ready <= 0;`
255			`x_rdy_cont_ready <= 0;`
256			`end`
257			`endcase`
258			`end`
259			`//save the previous primative`
260			`else begin`
261			`prev_prim <= rx_din;`
262			`//previous primative doesn't equal current primitive`
263			`cont_detect <= 0;`
264			`hold_cont_ready <= 0;`
265			`holda_cont_ready <= 0;`
266			`pmreq_p_cont_ready <= 0;`
267			`pmreq_s_cont_ready <= 0;`
268			`r_err_cont_ready <= 0;`
269			`r_ip_cont_ready <= 0;`
270			`r_ok_cont_ready <= 0;`
271			`r_rdy_cont_ready <= 0;`
272			`sync_cont_ready <= 0;`
273			`wtrm_cont_ready <= 0;`
274			`x_rdy_cont_ready <= 0;`
275
276			`end`
277			`end`
278			`if (!rx_isk[0] && !cont_detect) begin`
279			`cont_detect <= 0;`
280			`hold_cont_ready <= 0;`
281			`holda_cont_ready <= 0;`
282			`pmreq_p_cont_ready <= 0;`
283			`pmreq_s_cont_ready <= 0;`
284			`r_err_cont_ready <= 0;`
285			`r_ip_cont_ready <= 0;`
286			`r_ok_cont_ready <= 0;`
287			`r_rdy_cont_ready <= 0;`
288			`sync_cont_ready <= 0;`
289			`wtrm_cont_ready <= 0;`
290			`x_rdy_cont_ready <= 0;`
291			`end`
292			`end`
293			`end`
294			`end`
295
296
297			`//Cont Generator`
298			`always @ (posedge clk) begin`
299			`if (rst \|\| !xmit_cont_en) begin`
300			`tx_prev_prim <= 0;`
301			`tx_cont_enable <= 0;`
302			`tx_cont_sent <= 0;`
303			`send_cont <= 0;`
304			`end`
305			`else begin`
306			`if (phy_ready) begin`
307
308			`send_cont <= 0;`
309
310			`if (ll_tx_isk) begin`
311
312			`//reset everything because the previous primative is not equal to the current one`
313			`if (tx_prev_prim != ll_tx_din) begin`
314			`send_cont <= 0;`
315			`tx_cont_sent <= 0;`
316			`tx_cont_enable <= 0;`
317			`end`
318			`else begin`
319
320			`//see if we need to send the cont primative`
321			`if (tx_cont_enable && send_cont) begin`
322			`tx_cont_sent <= 1;`
323			`end`
324
325			`//previous primative == current primative`
326			`case (tx_prev_prim)`
327			`PRIM_SYNC : begin
328			`tx_cont_enable <= 1;`
329			`if (!tx_cont_sent && !send_cont) begin`
330			`send_cont <= 1;`
331			`end`
332			`end`
333			`PRIM_R_RDY : begin
334			`tx_cont_enable <= 1;`
335			`if (!tx_cont_sent && !send_cont) begin`
336			`send_cont <= 1;`
337			`end`
338			`end`
339			`PRIM_R_IP : begin
340			`tx_cont_enable <= 1;`
341			`if (!tx_cont_sent && !send_cont) begin`
342			`send_cont <= 1;`
343			`end`
344			`end`
345			`PRIM_R_ERR : begin
346			`tx_cont_enable <= 1;`
347			`if (!tx_cont_sent && !send_cont) begin`
348			`send_cont <= 1;`
349			`end`
350			`end`
351			`PRIM_R_OK : begin
352			`tx_cont_enable <= 1;`
353			`if (!tx_cont_sent && !send_cont) begin`
354			`send_cont <= 1;`
355			`end`
356			`end`
357			`PRIM_X_RDY : begin
358			`tx_cont_enable <= 1;`
359			`if (!tx_cont_sent && !send_cont) begin`
360			`send_cont <= 1;`
361			`end`
362			`end`
363			`PRIM_WTRM : begin
364			`tx_cont_enable <= 1;`
365			`if (!tx_cont_sent && !send_cont) begin`
366			`send_cont <= 1;`
367			`end`
368			`end`
369			`PRIM_HOLD : begin
370			`tx_cont_enable <= 1;`
371			`if (!tx_cont_sent && !send_cont) begin`
372			`send_cont <= 1;`
373			`end`
374			`end`
375			`PRIM_HOLDA : begin
376			`tx_cont_enable <= 1;`
377			`if (!tx_cont_sent && !send_cont) begin`
378			`send_cont <= 1;`
379			`end`
380			`end`
381			`PRIM_PREQ_S : begin
382			`tx_cont_enable <= 1;`
383			`if (!tx_cont_sent && !send_cont) begin`
384			`send_cont <= 1;`
385			`end`
386			`end`
387			`PRIM_PREQ_P : begin
388			`tx_cont_enable <= 1;`
389			`if (!tx_cont_sent && !send_cont) begin`
390			`send_cont <= 1;`
391			`end`
392			`end`
393			`default: begin`
394			`send_cont <= 0;`
395			`tx_cont_enable <= 0;`
396			`tx_cont_sent <= 0;`
397			`end`
398			`endcase`
399			`end`
400			`end`
401			`else begin`
402			`//it is not a k value so don't read it`
403			`tx_prev_prim <= 0;`
404			`end`
405			`//k value record the PRIM`
406			`tx_prev_prim <= ll_tx_din;`
407
408			`if (last_prim) begin`
409			`tx_cont_enable <= 0;`
410			`end`
411			`end`
412			`end`
413			`end`
414
415
416
417			`endmodule`
418