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[/] [nysa_sata/] [trunk/] [sim/] [data_test2.v] - Blame information for rev 2

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module data_test2 (
  input                 rst,            //reset
  input                 clk,
 
  output  reg           din_stb,
  input         [1:0]   din_ready,
  output  reg   [1:0]   din_activate,
  output  reg   [31:0]  din,
  input         [23:0]  din_size,
 
  input                 dout_ready,
  output  reg           dout_activate,
  input         [31:0]  dout,
  output  reg           dout_stb,
  input         [23:0]  dout_size,
 
  output  reg           count_error,
  output  reg           incorrect_data,
  output  reg   [23:0]  count_detected,
  output  reg   [31:0]  detected_value
 
);
 
//Parameters
//Registers/Wires
reg             [31:0]  write_count;
reg             [31:0]  read_count;
//Submodules
//Asynchronous Logic
//Synchronous Logic
 
always @ (posedge clk) begin
  if (rst) begin
    din_stb             <=  0;
    din_activate        <=  0;
    din                 <=  0;
    write_count         <=  0;
 
    dout_activate       <=  0;
    dout_stb            <=  0;
    read_count          <=  0;
 
    count_error         <=  0;
    incorrect_data      <=  0;
    detected_value      <=  0;
    count_detected      <=  0;
  end
  else begin
    din_stb             <=  0;
    dout_stb            <=  0;
    count_error         <=  0;
    incorrect_data      <=  0;
 
    if ((din_ready > 0) && (din_activate == 0)) begin
      write_count       <=  0;
      din               <=  0;
      if (din_ready[0]) begin
        din_activate[0] <=  1;
      end
      else begin
        din_activate[1] <=  1;
      end
    end
    else if (din_activate != 0) begin
      if (write_count < din_size) begin
        din_stb         <=  1;
        din             <=  write_count;
        write_count     <=  write_count + 1;
      end
      else begin
        din_activate    <=  0;
      end
    end
 
    if (dout_ready && !dout_activate) begin
      read_count        <=  0;
      dout_activate     <=  1;
      if (dout_size != 24'h0800) begin
        count_error     <=  1;
        count_detected  <=  dout_size;
      end
    end
    else if (dout_activate) begin
      if (read_count < dout_size) begin
        dout_stb        <=  1;
        read_count      <=  read_count + 1;
      end
      else begin
        dout_activate   <=  0;
      end
 
      //Error Detection
      if (read_count > 0) begin
        if (dout !=  read_count - 1) begin
          incorrect_data  <=  1;
          count_detected  <=  read_count[23:0];
          detected_value  <=  dout;
        end
      end
      else begin
        if (dout != 0) begin
          incorrect_data  <=  1;
          count_detected  <=  read_count[23:0];
          detected_value  <=  dout;
        end
      end
    end
  end
end
 
endmodule

Line No.	Rev	Author	Line
1	2	cospan	`module data_test2 (`
2			`input rst, //reset`
3			`input clk,`
4
5			`output reg din_stb,`
6			`input [1:0] din_ready,`
7			`output reg [1:0] din_activate,`
8			`output reg [31:0] din,`
9			`input [23:0] din_size,`
10
11			`input dout_ready,`
12			`output reg dout_activate,`
13			`input [31:0] dout,`
14			`output reg dout_stb,`
15			`input [23:0] dout_size,`
16
17			`output reg count_error,`
18			`output reg incorrect_data,`
19			`output reg [23:0] count_detected,`
20			`output reg [31:0] detected_value`
21
22			`);`
23
24			`//Parameters`
25			`//Registers/Wires`
26			`reg [31:0] write_count;`
27			`reg [31:0] read_count;`
28			`//Submodules`
29			`//Asynchronous Logic`
30			`//Synchronous Logic`
31
32			`always @ (posedge clk) begin`
33			`if (rst) begin`
34			`din_stb <= 0;`
35			`din_activate <= 0;`
36			`din <= 0;`
37			`write_count <= 0;`
38
39			`dout_activate <= 0;`
40			`dout_stb <= 0;`
41			`read_count <= 0;`
42
43			`count_error <= 0;`
44			`incorrect_data <= 0;`
45			`detected_value <= 0;`
46			`count_detected <= 0;`
47			`end`
48			`else begin`
49			`din_stb <= 0;`
50			`dout_stb <= 0;`
51			`count_error <= 0;`
52			`incorrect_data <= 0;`
53
54			`if ((din_ready > 0) && (din_activate == 0)) begin`
55			`write_count <= 0;`
56			`din <= 0;`
57			`if (din_ready[0]) begin`
58			`din_activate[0] <= 1;`
59			`end`
60			`else begin`
61			`din_activate[1] <= 1;`
62			`end`
63			`end`
64			`else if (din_activate != 0) begin`
65			`if (write_count < din_size) begin`
66			`din_stb <= 1;`
67			`din <= write_count;`
68			`write_count <= write_count + 1;`
69			`end`
70			`else begin`
71			`din_activate <= 0;`
72			`end`
73			`end`
74
75			`if (dout_ready && !dout_activate) begin`
76			`read_count <= 0;`
77			`dout_activate <= 1;`
78			`if (dout_size != 24'h0800) begin`
79			`count_error <= 1;`
80			`count_detected <= dout_size;`
81			`end`
82			`end`
83			`else if (dout_activate) begin`
84			`if (read_count < dout_size) begin`
85			`dout_stb <= 1;`
86			`read_count <= read_count + 1;`
87			`end`
88			`else begin`
89			`dout_activate <= 0;`
90			`end`
91
92			`//Error Detection`
93			`if (read_count > 0) begin`
94			`if (dout != read_count - 1) begin`
95			`incorrect_data <= 1;`
96			`count_detected <= read_count[23:0];`
97			`detected_value <= dout;`
98			`end`
99			`end`
100			`else begin`
101			`if (dout != 0) begin`
102			`incorrect_data <= 1;`
103			`count_detected <= read_count[23:0];`
104			`detected_value <= dout;`
105			`end`
106			`end`
107			`end`
108			`end`
109			`end`
110
111			`endmodule`

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[/] [nysa_sata/] [trunk/] [sim/] [data_test2.v] - Blame information for rev 2