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[/] [nysa_sata/] [trunk/] [sim/] [faux_sata_hd_command_layer.v] - Blame information for rev 2

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1 2 cospan 
//faux_hd_command_layer.v
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/*
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Distributed under the MIT license.
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Copyright (c) 2011 Dave McCoy (dave.mccoy@cospandesign.com)
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Permission is hereby granted, free of charge, to any person obtaining a copy of
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this software and associated documentation files (the "Software"), to deal in
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the Software without restriction, including without limitation the rights to
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use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is furnished to do
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so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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*/
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module faux_hd_command_layer (
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input               rst,            //reset
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input               clk,
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output              command_layer_ready,
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output              command_layer_busy,
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output              hd_read_from_host,
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output      [31:0]  hd_data_from_host,
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output              hd_write_to_host,
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input       [31:0]  hd_data_to_host,
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input               transport_layer_ready,
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output  reg         send_reg_stb,
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output  reg         send_dma_act_stb,
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output  reg         send_data_stb,
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output  reg         send_pio_stb,
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output  reg         send_dev_bits_stb,
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input               remote_abort,
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input               xmit_error,
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input               read_crc_fail,
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input               h2d_reg_stb,
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input               h2d_data_stb,
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input               pio_request,
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output reg   [15:0] pio_transfer_count,
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output reg          pio_direction,
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output reg   [7:0]  pio_e_status,
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//FIS Structure
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input        [7:0]  h2d_command,
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input        [15:0] h2d_features,
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input               h2d_cmd_bit,
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input        [3:0]  h2d_port_mult,
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input        [7:0]  h2d_control,
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input        [7:0]  h2d_device,
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input        [47:0] h2d_lba,
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input        [15:0] h2d_sector_count,
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output  reg         d2h_interrupt,
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output  reg         d2h_notification,
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output  reg  [7:0]  d2h_status,
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output  reg  [7:0]  d2h_error,
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output  reg  [3:0]  d2h_port_mult,
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output  reg  [7:0]  d2h_device,
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output  reg  [47:0] d2h_lba,
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output  reg  [15:0] d2h_sector_count,
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//command layer data interface
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input               cl_if_strobe,
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output      [31:0]  cl_if_data,
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output              cl_if_ready,
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input               cl_if_activate,
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output      [23:0]  cl_if_size,
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input               cl_of_strobe,
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input       [31:0]  cl_of_data,
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output      [1:0]   cl_of_ready,
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input       [1:0]   cl_of_activate,
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output      [23:0]  cl_of_size,
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output      [3:0]   cl_state
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);
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//Parameters
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parameter SLEEP_START       = 4'h0;
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parameter SEND_DIAGNOSTICS  = 4'h1;
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parameter IDLE              = 4'h2;
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parameter DMA_READY         = 4'h3;
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parameter READ_DATA         = 4'h4;
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parameter SEND_DATA         = 4'h5;
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parameter READ_IN_PROGRESS  = 4'h6;
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parameter SEND_STATUS       = 4'h7;
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//Registers/Wires
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reg         [3:0]   state               = SLEEP_START;
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wire                idle;
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reg         [8:0]   byte_count          = 0;
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reg         [15:0]  sector_count        = 0;
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reg         [15:0]  sector_size         = 16'h0000;
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reg         [15:0]  sleep_count         = 0;
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reg         [15:0]  sleep_size          = 1000;
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wire                soft_reset;
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//Asynchronous Logic
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assign              idle                = (state == IDLE);
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assign              command_layer_busy  = !idle;
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assign              command_layer_ready = idle;
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//Short circuit the ping pong fifos
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assign              hd_read_from_host   = cl_of_strobe;
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assign              hd_data_from_host   = cl_of_data;
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assign              cl_of_ready         = 1;
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assign              cl_of_size          = 2048;
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assign              hd_write_to_host    = cl_if_strobe;
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assign              cl_if_data          = hd_data_to_host;
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assign              cl_if_ready         = 1;
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assign              cl_if_size          = 24'h0100;
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assign              soft_reset          = h2d_control[`CONTROL_SRST_BIT];
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assign              cl_state            = state;
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//Synchronous Logic
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always @ (posedge clk) begin
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  if (rst) begin
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    state                               <=  SLEEP_START;
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    send_reg_stb                        <=  0;
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    send_dma_act_stb                    <=  0;
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    send_data_stb                       <=  0;
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    send_pio_stb                        <=  0;
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    send_dev_bits_stb                   <=  0;
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    sector_count                        <=  0;
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    sector_size                         <=  1000;
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    sleep_count                         <=  0;
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    sleep_size                          <=  1000;
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    pio_transfer_count                  <=  0;
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    pio_direction                       <=  0;
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    pio_e_status                        <=  0;
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    d2h_interrupt                       <=  0;
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    d2h_notification                    <=  0;
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    d2h_status                          <=  8'h50;
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    d2h_error                           <=  1;
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    d2h_port_mult                       <=  0;
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    d2h_lba                             <=  1;
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    d2h_sector_count                    <=  1;
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    d2h_device                          <=  0;
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    byte_count                          <=  0;
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  end
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  else begin
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    //Strobe Lines
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    send_reg_stb                        <=  0;
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    send_dma_act_stb                    <=  0;
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    send_data_stb                       <=  0;
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    send_pio_stb                        <=  0;
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    send_dev_bits_stb                   <=  0;
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    if (soft_reset) begin
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      state                             <=  SLEEP_START;
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      sleep_count                       <=  0;
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      sleep_size                        <=  1000;
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    end
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    case (state)
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      SLEEP_START: begin
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        if (sleep_count  < sleep_size) begin
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          sleep_count                   <=  sleep_count + 1;
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        end
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        else begin
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          state                         <=  SEND_DIAGNOSTICS;
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        end
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      end
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      SEND_DIAGNOSTICS: begin
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        send_reg_stb                    <=  1;
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        state                           <=  IDLE;
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      end
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      IDLE: begin
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        if (h2d_reg_stb) begin
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          if (h2d_cmd_bit) begin
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            d2h_lba                     <=  h2d_lba;
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            d2h_sector_count            <=  h2d_sector_count;
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            sector_size                 <=  h2d_sector_count;
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            case (h2d_command)
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              `COMMAND_DMA_READ_EX: begin
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                //send_data_stb           <=  1;
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                sector_count            <=  0;
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                sector_size             <=  h2d_sector_count;
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                state                   <=  SEND_DATA;
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              end
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              `COMMAND_DMA_WRITE_EX: begin
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                send_dma_act_stb        <=  1;
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                sector_count            <=  0;
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                sector_size             <=  h2d_sector_count;
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                state                   <=  DMA_READY;
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              end
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              default: begin
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                //unrecognized command
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                $display ("fcl: Unrecognized command from host");
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              end
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            endcase
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          end
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        end
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      end
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      DMA_READY: begin
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        if (transport_layer_ready) begin
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          send_dma_act_stb          <=  1;
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          byte_count                <=  0;
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          state                     <=  READ_DATA;
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        end
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      end
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      READ_DATA: begin
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        if (cl_of_activate && cl_of_strobe) begin
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          byte_count                <=  byte_count + 4;
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        end
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        if(byte_count == 508) begin
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          sector_count              <=  sector_count + 1;
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        end
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        if (h2d_data_stb) begin
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          if (sector_count  <  sector_size) begin
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            state                   <=  DMA_READY;
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          end
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          else begin
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            state                   <=  SEND_STATUS;
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          end
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        end
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      end
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      SEND_DATA: begin
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        if (transport_layer_ready) begin
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          sector_count              <=  sector_count + 1;
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          send_data_stb             <=  1;
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          state                     <=  READ_IN_PROGRESS;
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          //state                     <=  SEND_STATUS;
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        end
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      end
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      READ_IN_PROGRESS: begin
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        if (!transport_layer_ready) begin
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            state                   <= SEND_STATUS;
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        end
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        //if (sector_count < sector_size) begin
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        //  state                     <=  SEND_DATA;
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        //end
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        //else begin
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        //  if (transport_layer_ready) begin
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        //    send_reg_stb            <=  1;
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        //    //Send a done register
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        //    state                   <=  SEND_STATUS;
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        //  end
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        //end
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      end
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      SEND_STATUS: begin
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        if (transport_layer_ready) begin
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          send_reg_stb            <=  1;
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          //Send a done register
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          state                   <=  IDLE;
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        end
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      end
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      default: begin
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        $display ("fcl: Entered illegal state, restart");
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        state                       <=  SLEEP_START;
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        sleep_count                 <=  0;
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        sleep_size                  <=  1000;
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      end
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    endcase
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  end
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end
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endmodule

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