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[/] [nysa_sata/] [trunk/] [sim/] [faux_sata_hd_phy.v] - Blame information for rev 3

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//faux_sata_hd_phy.v
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/*
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Distributed under the MIT license.
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Copyright (c) 2011 Dave McCoy (dave.mccoy@cospandesign.com)
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Permission is hereby granted, free of charge, to any person obtaining a copy of
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this software and associated documentation files (the "Software"), to deal in
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the Software without restriction, including without limitation the rights to
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use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
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of the Software, and to permit persons to whom the Software is furnished to do
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so, subject to the following conditions:
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The above copyright notice and this permission notice shall be included in all
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copies or substantial portions of the Software.
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THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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SOFTWARE.
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*/
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`include "sata_defines.v"
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module faux_sata_hd_phy (
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//Inputs/Outputs
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input               rst,              //reset
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input               clk,
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//Data Interface
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output  reg [31:0]  tx_dout,
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output  reg         tx_is_k,
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output  reg         tx_set_elec_idle,
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output  reg         rx_byte_is_aligned,
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input       [31:0]  rx_din,
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input       [3:0]   rx_is_k,
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input               rx_is_elec_idle,
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input               comm_reset_detect,
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input               comm_wake_detect,
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output  reg         tx_comm_reset,
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output  reg         tx_comm_wake,
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output      [3:0]   lax_state,
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output  reg         hd_ready,
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output              phy_ready
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);
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//Parameters
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parameter           IDLE                  = 4'h0;
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parameter           WAIT_FOR_NO_RESET     = 4'h1;
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parameter           SEND_INIT             = 4'h2;
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parameter           WAIT_FOR_WAKE         = 4'h3;
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parameter           WAIT_FOR_NO_WAKE      = 4'h4;
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parameter           SEND_WAKE             = 4'h5;
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parameter           STOP_SEND_WAKE        = 4'h6;
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parameter           SEND_CONFIGURE_END    = 4'h7;
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parameter           WAIT_FOR_DIALTONE     = 4'h8;
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parameter           SEND_ALIGN            = 4'h9;
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parameter           WAIT_FOR_ALIGN        = 4'hA;
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parameter           READY                 = 4'hB;
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parameter           SEND_FIRST_ALIGNMENT  = 4'hC;
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parameter           SEND_SECOND_ALIGNMENT = 4'hD;
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parameter           INITIALIZE_TIMEOUT         = 100;
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//Registers/Wires
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reg         [3:0]   state = IDLE;
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reg         [31:0]  timer;
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reg         [7:0]   align_count;
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wire                align_detected;
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wire                dialtone_detected;
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wire                timeout;
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//Sub Modules
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//Asynchronous Logic
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assign              lax_state         = state;
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assign              align_detected    = ((rx_is_k > 0) && (rx_din == `PRIM_ALIGN));
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assign              dialtone_detected = ((rx_is_k == 0) && (rx_din == `DIALTONE));
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assign              timeout           = (timer == 0);
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assign              phy_ready         = (state == READY);
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//Synchronous Logic
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always @ (posedge clk) begin
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  if (rst) begin
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    state                   <=  IDLE;
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    tx_dout                 <=  0;
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    tx_is_k                 <=  0;
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    tx_set_elec_idle        <=  1;
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    timer                   <=  0;
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    hd_ready                <=  0;
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    rx_byte_is_aligned      <=  0;
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    align_count             <=  0;
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  end
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  else begin
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    tx_comm_reset           <=  0;
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    tx_comm_wake            <=  0;
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    rx_byte_is_aligned      <=  0;
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    if (state == READY) begin
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      align_count           <=  align_count + 1;
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    end
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    if (timer > 0) begin
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      timer                 <=  timer - 1;
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    end
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    if ((comm_reset_detect) && (state > WAIT_FOR_NO_RESET)) begin
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      $display("faux_sata_hd: Asynchronous RESET detected");
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      align_count           <=  0;
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      hd_ready              <=  0;
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      state                 <=  WAIT_FOR_NO_RESET;
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    end
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    case (state)
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      IDLE: begin
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        align_count         <=  0;
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        hd_ready            <=  0;
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        tx_set_elec_idle    <=  1;
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        if (comm_reset_detect) begin
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          //detected a reset from the host
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          $display("faux_sata_hd: RESET detected");
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          state             <=  WAIT_FOR_NO_RESET;
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        end
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      end
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      WAIT_FOR_NO_RESET: begin
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        if (!comm_reset_detect) begin
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          //host stopped sending reset
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          $display("faux_sata_hd: RESET deasserted");
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          hd_ready          <=  0;
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          state             <=  SEND_INIT;
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        end
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      end
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      SEND_INIT: begin
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//XXX: I may need to send more than one of these
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        $display("faux_sata_hd: send INIT");
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        tx_comm_reset       <=  1;
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        state               <=  WAIT_FOR_WAKE;
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      end
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      WAIT_FOR_WAKE: begin
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        if (comm_wake_detect) begin
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          $display ("faux_sata_hd: WAKE detected");
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          state             <=  WAIT_FOR_NO_WAKE;
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        end
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      end
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      WAIT_FOR_NO_WAKE: begin
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        if (!comm_wake_detect) begin
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          $display ("faux_sata_hd: WAKE deasserted");
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          state             <=  SEND_WAKE;
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        end
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      end
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      SEND_WAKE: begin
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        $display ("faux_sata_hd: send WAKE");
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        tx_comm_wake        <=  1;
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        state               <=  STOP_SEND_WAKE;
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      end
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      STOP_SEND_WAKE: begin
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        $display ("faux_sata_hd: stop sending WAKE");
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        state               <=  WAIT_FOR_DIALTONE;
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      end
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      WAIT_FOR_DIALTONE: begin
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        if (dialtone_detected) begin
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          $display ("faux_sata_hd: detected dialtone");
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          state             <=  SEND_ALIGN;
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        end
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      end
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      SEND_ALIGN: begin
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        $display ("faux_sata_hd: send aligns");
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        tx_set_elec_idle    <=  0;
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        tx_dout             <=  `PRIM_ALIGN;
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        tx_is_k             <=  1;
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        state               <=  WAIT_FOR_ALIGN;
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        timer               <=  32'h`INITIALIZE_TIMEOUT;
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        rx_byte_is_aligned  <=  1;
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      end
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      WAIT_FOR_ALIGN: begin
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        tx_is_k             <=  1;
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        tx_dout             <=  `PRIM_ALIGN;
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        rx_byte_is_aligned  <=  1;
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        //$display ("faux_sata_hd: waiting for aligns...");
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        //$display ("rx din: %h, k: %h", rx_din, rx_is_k);
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        if (align_detected) begin
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          $display ("faux_sata_hd: detected ALIGN primitive from host");
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          $display ("faux_sata_hd: Ready");
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          tx_dout           <=  `PRIM_ALIGN;
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          tx_is_k           <=  1;
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          timer             <=  0;
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          state             <=  READY;
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        end
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        else if (timeout) begin
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          $display ("faux_sata_hd: Timeout while waiting for an alignment from the host");
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          state             <=  IDLE;
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        end
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      end
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      READY: begin
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        hd_ready            <=  1;
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        rx_byte_is_aligned  <=  1;
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        tx_is_k             <=  1;
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        tx_dout             <=  `PRIM_SYNC;
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        if (align_count == 255) begin
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          tx_dout           <=  `PRIM_ALIGN;
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          state             <=  SEND_FIRST_ALIGNMENT;
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        end
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      end
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      SEND_FIRST_ALIGNMENT: begin
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        rx_byte_is_aligned  <=  1;
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        tx_is_k             <=  1;
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        tx_dout             <=  `PRIM_ALIGN;
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        state               <=  SEND_SECOND_ALIGNMENT;
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      end
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      SEND_SECOND_ALIGNMENT: begin
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        rx_byte_is_aligned  <=  1;
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        tx_is_k             <=  1;
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        tx_dout             <=  `PRIM_ALIGN;
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        state               <=  READY;
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      end
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      default: begin
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        $display ("faux_sata_hd: In undefined state!");
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        state               <=  IDLE;
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      end
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    endcase
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  end
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end
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endmodule

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