OpenCores
URL https://opencores.org/ocsvn/nysa_sata/nysa_sata/trunk

Subversion Repositories nysa_sata

[/] [nysa_sata/] [trunk/] [sim/] [sata_defines.v] - Blame information for rev 3

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 2 cospan
//sata_defines.v
2
/*
3
Distributed under the MIT license.
4
Copyright (c) 2011 Dave McCoy (dave.mccoy@cospandesign.com)
5
 
6
Permission is hereby granted, free of charge, to any person obtaining a copy of
7
this software and associated documentation files (the "Software"), to deal in
8
the Software without restriction, including without limitation the rights to
9
use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies
10
of the Software, and to permit persons to whom the Software is furnished to do
11
so, subject to the following conditions:
12
 
13
The above copyright notice and this permission notice shall be included in all
14
copies or substantial portions of the Software.
15
 
16
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
19
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22
SOFTWARE.
23
*/
24
 
25
`ifndef __SATA_DEFINES__
26
`define __SATA_DEFINES__
27
 
28
//Presuming 75MHz clock
29 3 cospan
`define SATA_CLOCK_RATE            (75000000)
30 2 cospan
// 1 / 880uS = 1136 times per seconds
31
`define NORMAL_TIMEOUT        (1000000) / 880
32
 
33
//Input/Output buffer sizes
34
`define DATA_SIZE             32
35
//2048 dwords
36
`define FIFO_ADDRESS_WIDTH    11
37
 
38
//880uS
39 3 cospan
//`define INITIALIZE_TIMEOUT    ((`SATA_CLOCK_RATE) / (`NORMAL_TIMEOUT))
40 2 cospan
`define INITIALIZE_TIMEOUT    66000
41
//`define SEND_WAKE_TIMEOUT     4E
42
 
43
`define PRIM_ALIGN            32'h7B4A4ABC
44
`define PRIM_SYNC             32'hB5B5957C
45
`define PRIM_R_RDY            32'h4A4A957C
46
`define PRIM_R_IP             32'h5555B57C
47
`define PRIM_R_OK             32'h3535B57C
48
`define PRIM_R_ERR            32'h5656B57C
49
`define PRIM_SOF              32'h3737B57C
50
`define PRIM_EOF              32'hD5D5B57C
51
`define PRIM_X_RDY            32'h5757B57C
52
`define PRIM_WTRM             32'h5858B57C
53
`define PRIM_CONT             32'h9999AA7C
54
`define PRIM_HOLD             32'hD5D5AA7C
55
`define PRIM_HOLDA            32'h9595AA7C
56
`define PRIM_PMNACK           32'hF5F5957C
57
`define PRIM_PMACK            32'h9595957C
58
`define PRIM_PREQ_P           32'h1717B57C
59
`define PRIM_PREQ_S           32'h7575957C
60
 
61
 
62
`define DIALTONE              32'h4A4A4A4A
63
 
64
 
65
//FIS Types
66
`define FIS_H2D_REG           8'h27
67
`define FIS_D2H_REG           8'h34
68
`define FIS_DMA_ACT           8'h39
69
`define FIS_DMA_SETUP         8'h41
70
`define FIS_DATA              8'h46
71
`define FIS_BIST              8'h58
72
`define FIS_PIO_SETUP         8'h5F
73
`define FIS_SET_DEV_BITS      8'hA1
74
 
75
//Transport Data Direction
76
`define DATA_OUT              0
77
`define DATA_IN               1
78
 
79
//Command Types
80
`define COMMAND_DMA_READ_EX     8'h25
81
`define COMMAND_DMA_WRITE_EX    8'h35
82
`define COMMAND_NOP             8'h00
83
`define COMMNAD_IDENTIFY_DEVICE 8'hEC
84
 
85
//Sizes
86
`define FIS_H2D_REG_SIZE        24'h5
87
`define FIS_D2H_REG_SIZE        24'h5
88
`define FIS_PIO_SETUP_SIZE      24'h5
89
`define FIS_DMA_SETUP_SIZE      24'h7
90
`define FIS_DMA_ACT_SIZE        24'h1
91
`define FIS_SET_DEV_BITS_SIZE   24'h2
92
 
93
//Register FIS Bits
94
`define STATUS_BUSY_BIT       7
95
`define STATUS_DRQ_BIT        3
96
`define STATUS_ERR_BIT        0
97
 
98
 
99
`define CONTROL_SRST_BIT      2
100
 
101
`define H2D_REG_COMMAND       1
102
`define H2D_REG_CONTROL       0
103
 
104
//Not really sure what to put in the features register
105
`define D2H_REG_FEATURES      16'h0000
106
`define D2H_REG_DEVICE        8'h40
107
 
108
`define D2H_REG_DRQ           1
109
`define D2H_REG_ERR           1
110
 
111
 
112
`endif

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.