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<!-- BODY --><b><font size=+2 face="Helvetica, Arial"
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color=#bf0000>Project Name:&nbsp;</font></b>
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<p><b><font size=+2 face="Helvetica, Arial"
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color=#bf0000>OPENCORES Application Board 1 (OAB1)</font></b></p>
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<h1><font size="4">Introduction</font></h1>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">As
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you know, we have lots of free IP cores here, and we’ll have more coming soon.
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We have to use these cores otherwise they are invaluable. For this reason the
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idea of designing serials and open design boards are going to be available for
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any designers around the world. <o:p>
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</o:p>
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</span></p>
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<h1><span style="mso-bidi-font-size: 12.0pt"><font size="4">Objective<o:p>
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</o:p>
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</font></span></h1>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">This
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project is intended to: <o:p>
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</o:p>
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</span></p>
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<ul>
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  <li>
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    <p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">To
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    design schematic can deal with analog signal and transport through Ethernet.
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    <o:p>
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    </o:p>
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    </span></li>
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  <li>
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    <p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">To
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    implementation CPU core and Ethernet core to one FPGA chip <o:p>
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    </o:p>
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    </span></li>
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  <li>
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    <p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">To
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    program the necessary operation system and application software to achieve
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    the goal.<o:p>
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    </o:p>
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    </span></li>
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  <li>
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    <p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">To
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    build the prototype board.<o:p>
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    </o:p>
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    </span></li>
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  <li>
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    <p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">To
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    do the test for all functions.<o:p>
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    </o:p>
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    </span></li>
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</ul>
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<h1><font size="4"><span style="font-family: Arial; mso-bidi-font-size: 12.0pt">&nbsp;</span>Design
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Flow</font></h1>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">This
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project can be divided into two parts. The board design and the cores design.
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Anyone can use free or commercial tools to design and implement this project</span></p>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Board
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design flow can be done through four steps: <o:p>
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</o:p>
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</span></p>
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<ul>
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  <li>
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    <p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Block
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    Diagram design: I hope we use word 97+ for easy modify and exchange. <o:p>
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    </o:p>
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    </span></li>
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  <li>
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    <p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Schematic
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    entry: I will post schematic using PDF format. Anyone can also send me using
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    PDF, protel99se or Cadence format. <o:p>
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    </o:p>
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    </span></li>
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  <li>
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    <p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Layout
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    design: The final layout will use Allegro or Protel99se. <o:p>
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    </o:p>
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    </span></li>
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  <li>
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    <p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Board
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    implementation: This is the final step in the design where the designer
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    should work himself to produce his board unless we get funding or donation
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    from PCB manufactory.<o:p>
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    </o:p>
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    </span></li>
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</ul>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Cores
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design flow can be done through five steps: <o:p>
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</o:p>
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</span></p>
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<ul>
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  <li>
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    <p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Design
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    entry: Doesn’t matter the tools, we exchange only VHDL or Verilog codes. <o:p>
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    </o:p>
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    </span></li>
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  <li>
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    <p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Simulation:
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    I hope to use ModelSim or Active-HDL, but other tools also welcome.<o:p>
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    </o:p>
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    </span></li>
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  <li>
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    <p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Synthesis:
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    I hope to use FPGA express, but other tools also welcome.<o:p>
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    </o:p>
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    </span></li>
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  <li>
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    <p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Implementation:
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    I hope to use Xilinx FPGA.<o:p>
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    </o:p>
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    </span></li>
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  <li>
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    <p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Programming
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    Download: Using onboard parallel cable.<o:p>
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    </o:p>
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    </span></li>
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</ul>
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<h1><font size="4"><span style="font-family: Arial; mso-bidi-font-size: 12.0pt">&nbsp;</span>System
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Description</font></h1>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">This
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is the Board block diagram<br style="mso-special-character: line-break">
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<br style="mso-special-character: line-break">
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</span><span style="FONT-FAMILY: Verdana"><o:p>
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</o:p>
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</span><span style="FONT-FAMILY: Verdana"><o:p>
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 <img border="0" src="ver02.jpg" width="750" height="675"></o:p>
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</span></p>
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<p class="MsoNormal"><span style="FONT-FAMILY: Verdana"><span style="mso-spacerun: yes">&nbsp;&nbsp;
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</span>
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</span><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">The
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system is composed of 5 main blocks:<o:p>
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</o:p>
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</span></p>
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<ul>
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  <li>
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    <p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Xilinx
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    FPGA, PROM and parallel interface<o:p>
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    </o:p>
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    </span></li>
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  <li>
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    <p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">SRAM
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    circuit<o:p>
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    </o:p>
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    </span></li>
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  <li>
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    <p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">ADC
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    and DAC interface<o:p>
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    </o:p>
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    </span></li>
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  <li>
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    <p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Ethernet
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    interface<o:p>
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    </o:p>
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    </span></li>
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  <li>
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    <p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Power
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    and reset circuit<o:p>
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    </o:p>
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    </span></li>
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</ul>
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<h1><font size="4">Schematic Design</font></h1>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">TBD<o:p>
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</o:p>
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</span></p>
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<h1><font size="4">Layout Design</font></h1>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">TBD
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<o:p>
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</o:p>
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</span></p>
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<h1><font size="4">Current Status:</font></h1>
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<p style="mso-margin-top-alt: auto; mso-margin-bottom-alt: auto"><span style="font-size: 14pt; font-family: Arial; mso-bidi-font-size: 12.0pt">2001.8.20
376 
Upload Board block diagram <a href="ver01.JPG">version 0.1</a></span></p>
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<p style="mso-margin-top-alt: auto; mso-margin-bottom-alt: auto"><span style="font-size: 14pt; font-family: Arial; mso-bidi-font-size: 12.0pt">2001.8.21
378 
Upload Board block diagram <a href="ver02.jpg">version 0.2</a></span></p>
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<h1><font size="4">Maintainer(s):</font></h1>
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<h1><font size="3">Martin Jiang <a href="mailto:martinj@opencores.org"><span style="FONT-FAMILY: 'Times New Roman'; mso-bidi-font-family: Arial">martinj@opencores.org</span></a></font></h1>
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<h1><font size="4">Mailing-list:</font></h1>
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<p class="MsoNormal"><span style="FONT-FAMILY: Verdana"><a href="mailto:cores@opencores.org_NOSPAM">cores@opencores.org_NOSPAM</a><o:p>
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</o:p>
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</span></p>
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<h1><font size="4">References tools and links</font></h1>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt"><a href="http://xoscope.sourceforge.net/"><span style="mso-ascii-font-family: Arial; mso-hansi-font-family: Arial">Xscope
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home page</span></a> <o:p>
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</o:p>
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</span></p>
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<p class="MsoNormal"><span style="font-size: 14pt; font-family: Arial; mso-bidi-font-size: 12.0pt">SSM2141
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<a href="http://products.analog.com/products/info.asp?product=SSM2141">Datasheet</a></span></p>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">DAC8248
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<a href="http://products.analog.com/products/info.asp?product=DAC8248">Datasheet</a>
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</span></p>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">AD7854
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<a href="http://products.analog.com/products/info.asp?product=AD7854">Datasheet</a>
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</span></p>
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<p class="MsoNormal"><span style="font-size: 14pt; font-family: Arial; mso-bidi-font-size: 12.0pt">RTL8201</span><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">
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<a href="http://www.realtek.com.tw/htm/download/cgi/DLd1.cgi?model=rtl8201&amp;type=1"><span style="mso-ascii-font-family: Arial; mso-hansi-font-family: Arial">Datasheet</span></a><o:p></o:p>
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</span></p>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">PE68515
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<a href="http://www.pulseeng.com/pdf/H303.pdf">Datasheet</a>
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</span></p>
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<p class="MsoNormal"><span style="FONT-SIZE: 14pt; FONT-FAMILY: Arial; mso-bidi-font-size: 12.0pt">Xilinx
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Virtex-E <a href="http://www.xilinx.com/partinfo/ds022.htm"><span style="mso-ascii-font-family: Arial; mso-hansi-font-family: Arial">Datasheet</span></a><o:p>
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</o:p>
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</span></p>
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<p>
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<font size=+1><b>Acknowledgment</b></font>
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